From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: properly reenable gen8 pipe IRQs Date: Tue, 7 Oct 2014 22:58:45 +0300 Message-ID: <20141007195845.GE32511@intel.com> References: <1412709071-1886-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1412709071-1886-1-git-send-email-przanoni@gmail.com> Sender: stable-owner@vger.kernel.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Oct 07, 2014 at 04:11:10PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni >=20 > We were missing the pipe B/C vblank bits! Take a look at > gen8_de_irq_postinstall for a comparison. >=20 > This should fix a bunch of IGT tests. >=20 > There are a few more things we could improve on this code, but this > should be the minimal fix to unblock us. >=20 > Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=3D83640 > Testcase: igt/* > Cc: stable@vger.kernel.org > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_irq.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i= 915_irq.c > index b12c4c4..3bbdb9c 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3166,11 +3166,13 @@ static void gen8_irq_reset(struct drm_device = *dev) > =20 > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_pr= iv) > { > + uint32_t extra_iir =3D GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; extra_iir seems a bit weird as a name when this is about IER. Maybe uint32_t de_pipe_enables =3D ~dev_priv->de_irq_mask | ...; to better match gen8_de_irq_postinstall()? In any case now those reported vblank timeout failures at least make some sense, so even w/o that change: Reviewed-by: Ville Syrj=E4l=E4 But IIRC we had some vblank timeout reports on other platforms too (PNV maybe?). Wouldn't it be cute if this patch cured those too :) And I'll end with the rant of the day: Boy do I hate that stupid ~ we have to sprinkle around everywhere. Almo= st makes me wish someone would go and hide that in some special IMR regist= er access macro so we wouldn't have to invert bits all the time. > + > spin_lock_irq(&dev_priv->irq_lock); > GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], > - ~dev_priv->de_irq_mask[PIPE_B]); > + ~dev_priv->de_irq_mask[PIPE_B] | extra_iir); > GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], > - ~dev_priv->de_irq_mask[PIPE_C]); > + ~dev_priv->de_irq_mask[PIPE_C] | extra_iir); > spin_unlock_irq(&dev_priv->irq_lock); > } > =20 > --=20 > 2.1.1 >=20 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx --=20 Ville Syrj=E4l=E4 Intel OTC