From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 2/2] drm/i915: only run
 hsw_power_well_post_enable when really needed
Date: Tue, 7 Oct 2014 23:00:54 +0300
Message-ID: <20141007200054.GF32511@intel.com>
References: <1412709071-1886-1-git-send-email-przanoni@gmail.com>
 <1412709071-1886-2-git-send-email-przanoni@gmail.com>
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To: Paulo Zanoni <przanoni@gmail.com>
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On Tue, Oct 07, 2014 at 04:11:11PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> =

> Only run it after we actually enable the power well. When we're
> booting the machine there are cases where we run
> hsw_power_well_post_enable without really needing, and even though
> this is not causing any real bugs, it is unneeded and causes confusion
> to people debugging interrupts.
> =

> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Seems perfectly sensible.

Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> =

> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i9=
15/intel_runtime_pm.c
> index 36749b9..39c33e0 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -221,9 +221,9 @@ static void hsw_set_power_well(struct drm_i915_privat=
e *dev_priv,
>  			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
>  				      HSW_PWR_WELL_STATE_ENABLED), 20))
>  				DRM_ERROR("Timeout enabling power well\n");
> +			hsw_power_well_post_enable(dev_priv);
>  		}
>  =

> -		hsw_power_well_post_enable(dev_priv);
>  	} else {
>  		if (enable_requested) {
>  			I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
> -- =

> 2.1.1
> =

> _______________________________________________
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-- =

Ville Syrj=E4l=E4
Intel OTC