From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [RFC 4/7] drm/i915: Program PPS registers Date: Mon, 20 Oct 2014 19:28:22 +0300 Message-ID: <20141020162822.GY4284@intel.com> References: <1413809409-8569-1-git-send-email-vandana.kannan@intel.com> <1413809409-8569-5-git-send-email-vandana.kannan@intel.com> <20141020160848.GT26941@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C8D86E0D8 for ; Mon, 20 Oct 2014 09:29:32 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20141020160848.GT26941@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Oct 20, 2014 at 06:08:48PM +0200, Daniel Vetter wrote: > On Mon, Oct 20, 2014 at 06:20:06PM +0530, Vandana Kannan wrote: > > Actually set values into PPS related registers. This implementation is > > equivalent to intel_dp_panel_power_sequencer_registers where the values > > saved intially are written into registers. > > = > > Signed-off-by: Vandana Kannan > > --- > > drivers/gpu/drm/i915/intel_dp.c | 80 ++----------------------------= -------- > > drivers/gpu/drm/i915/intel_drv.h | 3 ++ > > drivers/gpu/drm/i915/intel_panel.c | 70 ++++++++++++++++++++++++++++++= +++ > > 3 files changed, 76 insertions(+), 77 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index a433c5f..ca11eb1 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -248,7 +248,7 @@ unpack_aux(uint32_t src, uint8_t *dst, int dst_byte= s) > > } > > = > > /* hrawclock is 1/4 the FSB frequency */ > > -static int > > +int > > intel_hrawclk(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > @@ -281,11 +281,6 @@ intel_hrawclk(struct drm_device *dev) > > } > > } > > = > > -static void > > -intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, > > - struct intel_dp *intel_dp, > > - struct edp_power_seq *out); > > - > > static void pps_lock(struct intel_dp *intel_dp) > > { > > struct intel_digital_port *intel_dig_port =3D dp_to_dig_port(intel_dp= ); > > @@ -4716,76 +4711,6 @@ static void intel_dp_init_panel_power_timestamps= (struct intel_dp *intel_dp) > > intel_dp->last_backlight_off =3D jiffies; > > } > > = > > -static void > > -intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, > > - struct intel_dp *intel_dp, > > - struct edp_power_seq *seq) > = > Hm, moving this function looks like it would be clearer as part of patch > 1? > = > Otherwise I've done a (very) quick read-through of your series and on a > high level it looks sane I think. So please sign someone up for the > detailed review (and make sure that person is aware of that AR) so I can > merge this. Would be nice if this series could be rebased on top of my VLV/CHV PPS series since I'd rather not redo that thing a third time. -- = Ville Syrj=E4l=E4 Intel OTC