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From: Daniel Vetter <daniel@ffwll.ch>
To: "Singh, Gaurav K" <gaurav.k.singh@intel.com>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>,
	intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 3/9] drm/i915: MIPI Port Ctrl related changes for dual link configuration
Date: Tue, 21 Oct 2014 14:12:54 +0200	[thread overview]
Message-ID: <20141021121254.GD26941@phenom.ffwll.local> (raw)
In-Reply-To: <5445FD86.4060300@intel.com>

On Tue, Oct 21, 2014 at 12:00:30PM +0530, Singh, Gaurav K wrote:
> 
> On 9/24/2014 2:57 PM, Jani Nikula wrote:
> >On Wed, 24 Sep 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> >>Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> >>Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> >>---
> >>  drivers/gpu/drm/i915/i915_reg.h            |    1 +
> >>  drivers/gpu/drm/i915/intel_dsi.c           |   53 ++++++++++++++++++++++------
> >>  drivers/gpu/drm/i915/intel_dsi.h           |    1 +
> >>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    1 +
> >>  4 files changed, 45 insertions(+), 11 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>index ad8179b..922d807 100644
> >>--- a/drivers/gpu/drm/i915/i915_reg.h
> >>+++ b/drivers/gpu/drm/i915/i915_reg.h
> >>@@ -6215,6 +6215,7 @@ enum punit_power_well {
> >>  #define  DPI_ENABLE					(1 << 31) /* A + B */
> >>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
> >>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
> >>+#define  DUAL_LINK_MODE_SHIFT				26
> >>  #define  DUAL_LINK_MODE_MASK				(1 << 26)
> >>  #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
> >>  #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
> >>diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> >>index e456ca9..3b1890e 100644
> >>--- a/drivers/gpu/drm/i915/intel_dsi.c
> >>+++ b/drivers/gpu/drm/i915/intel_dsi.c
> >>@@ -109,13 +109,31 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
> >>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> >>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> >>  	enum pipe pipe = intel_crtc->pipe;
> >>-	u32 temp;
> >>-
> >>-	/* assert ip_tg_enable signal */
> >>-	temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
> >>-	temp = temp | intel_dsi->port_bits;
> >>-	I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
> >>-	POSTING_READ(MIPI_PORT_CTRL(pipe));
> >>+	u32 temp, port_control = 0;
> >>+
> >>+	if (intel_dsi->dual_link) {
> >>+		port_control = (intel_dsi->dual_link - 1)
> >>+					<< DUAL_LINK_MODE_SHIFT;
> >>+		port_control |= pipe ? LANE_CONFIGURATION_DUAL_LINK_B :
> >>+					LANE_CONFIGURATION_DUAL_LINK_A;
> >>+		/*For Port A */
> >>+		temp = I915_READ(MIPI_PORT_CTRL(0));
> >>+		temp = temp | port_control;
> >>+		I915_WRITE(MIPI_PORT_CTRL(0), temp | DPI_ENABLE);
> >>+		POSTING_READ(MIPI_PORT_CTRL(0));
> >>+
> >>+		/* For Port C */
> >>+		temp = I915_READ(MIPI_PORT_CTRL(1));
> >>+		I915_WRITE(MIPI_PORT_CTRL(1), temp | DPI_ENABLE);
> >>+		POSTING_READ(MIPI_PORT_CTRL(1));
> >This calls for a cleanup in i915_reg.h for per port vs. per transcoder
> >registers. MIPI_PORT_CTRL(1) uses _TRANSCODER macro. We also have enum
> >port with PORT_C == 2. This gets confusing.
> 
> Are you suggesting to use _PORT macro instead of _TRANSCODER macro?

I think so, and given that we already have some offenders the existing
code should be converted with a prep patch first.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

  reply	other threads:[~2014-10-21 12:12 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-24  8:46 [PATCH 0/9] BYT DSI Dual Link Support Gaurav K Singh
2014-09-24  8:46 ` [PATCH 1/9] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
2014-09-24  8:46 ` [PATCH 2/9] drm/i915: MIPI Sequence to be sent to the DSI Controller based on the port no from VBT Gaurav K Singh
2014-09-24  8:46 ` [PATCH 3/9] drm/i915: MIPI Port Ctrl related changes for dual link configuration Gaurav K Singh
2014-09-24  9:27   ` Jani Nikula
2014-10-21  6:30     ` Singh, Gaurav K
2014-10-21 12:12       ` Daniel Vetter [this message]
2014-10-21 13:19         ` Jani Nikula
2014-09-24  8:46 ` [PATCH 4/9] drm/i915: Pixel Clock and pixel overlap related changes for dual link Configuration Gaurav K Singh
2014-09-24  9:23   ` Jani Nikula
2014-09-24  8:46 ` [PATCH 5/9] drm/i915: SHUTDOWN & Turn ON packets to be sent for both MIPI Ports in case of " Gaurav K Singh
2014-09-24  9:32   ` Jani Nikula
2014-09-25 12:54     ` Shobhit Kumar
2014-09-25 13:39       ` Jani Nikula
2014-09-25 14:22         ` Shobhit Kumar
2014-09-24  8:46 ` [PATCH 6/9] drm/i915: Dsipll clk to be enabled for DSI1 in case of dual link configuration Gaurav K Singh
2014-09-24  9:34   ` Jani Nikula
2014-09-24  8:46 ` [PATCH 7/9] drm/i915: MIPI Timings related changes for dual link Configuration Gaurav K Singh
2014-09-24  8:46 ` [PATCH 8/9] drm/i915: MIPI encoder disable " Gaurav K Singh
2014-09-24  8:46 ` [PATCH 9/9] drm/i915: MIPI Encoder enable related changes for dual link configuration Gaurav K Singh
2014-09-24  9:01 ` [PATCH 0/9] BYT DSI Dual Link Support Daniel Vetter
2014-09-25 12:47   ` Shobhit Kumar

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