From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/2] drm/i915/bdw: Setup global hardware status page in execlists mode Date: Fri, 24 Oct 2014 10:14:51 +0200 Message-ID: <20141024081451.GT26941@phenom.ffwll.local> References: <1414077886-19017-1-git-send-email-thomas.daniel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wg0-f46.google.com (mail-wg0-f46.google.com [74.125.82.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 104D66E010 for ; Fri, 24 Oct 2014 01:14:42 -0700 (PDT) Received: by mail-wg0-f46.google.com with SMTP id l18so537396wgh.17 for ; Fri, 24 Oct 2014 01:14:41 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1414077886-19017-1-git-send-email-thomas.daniel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Thomas Daniel Cc: intel-gfx@lists.freedesktop.org, shuang.he@linux.intel.com List-Id: intel-gfx@lists.freedesktop.org On Thu, Oct 23, 2014 at 04:24:46PM +0100, Thomas Daniel wrote: > Write HWS_PGA address even in execlists mode as the global hardware status > page is still required. This address was previously uninitialized and > HWSP writes would clobber whatever buffer happened to reside at GGTT > address 0. > > Issue: VIZ-2020 > Signed-off-by: Thomas Daniel > --- > drivers/gpu/drm/i915/intel_lrc.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 666cb28..ad36d66 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1678,6 +1678,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx, > uint32_t context_size; > struct intel_ringbuffer *ringbuf; > int ret; > + struct drm_i915_private *dev_priv = dev->dev_private; > > WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); > if (ctx->engine[ring->id].state) > @@ -1750,6 +1751,10 @@ int intel_lr_context_deferred_create(struct intel_context *ctx, > if (ring->status_page.page_addr == NULL) > return -ENOMEM; > ring->status_page.obj = ctx_obj; > + > + I915_WRITE(RING_HWS_PGA(ring->mmio_base), > + (u32)ring->status_page.gfx_addr); > + POSTING_READ(RING_HWS_PGA(ring->mmio_base)); So every time a random new contexts gets created we write a new value into the HWS_PGA register? Shouldn't this only be done when we set up the default/system context? -Daniel > } > > if (ring->id == RCS && !ctx->rcs_initialized) { > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch