From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Ignore SURFLIVE and flip counter when the GPU gets reset Date: Fri, 24 Oct 2014 15:50:16 +0300 Message-ID: <20141024125016.GB4284@intel.com> References: <1401215590-24141-1-git-send-email-ville.syrjala@linux.intel.com> <20140528121055.GC31610@nuc-i3427.alporthouse.com> <20141024124035.GA24617@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F5BA6E06F for ; Fri, 24 Oct 2014 05:50:24 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20141024124035.GA24617@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Oct 24, 2014 at 01:40:35PM +0100, Chris Wilson wrote: > On Wed, May 28, 2014 at 01:10:55PM +0100, Chris Wilson wrote: > > On Tue, May 27, 2014 at 09:33:09PM +0300, ville.syrjala@linux.intel.com= wrote: > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i= 915/intel_display.c > > > index 94ac51f..cb9dd8e 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -8895,6 +8895,10 @@ static bool page_flip_finished(struct intel_cr= tc *crtc) > > > struct drm_device *dev =3D crtc->base.dev; > > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > > = > > > + if (i915_reset_in_progress(&dev_priv->gpu_error) || > > > + crtc->reset_counter !=3D atomic_read(&dev_priv->gpu_error.reset= _counter)) > > > + return true; > > = > > I really don't like this. The reset_count is incremented when the reset > > starts, so we shouldn't get here with > > crtc->reset_counter =3D=3D gpu_error->reset_counter && reset_in_progres= s(). > > = > > I'd prefer this to be > > if (i915_has_reset(dev_priv, crtc->reset_counter)) return true; > > = > > with a guard when reading the gpu reset_counter: > > = > > ret =3D i915_get_reset_counter(dev_priv, &intel_crtc->reset_counter); > > if (ret) > > goto cleanup; > > = > > that does something like > > = > > static inline int i915_get_reset_counter(struct drm_i915_private *dev_= priv, > > int *value) > > { > > *value =3D atomic_read(dev_priv->gpu_error.reset_counter); > > if (*value & I915_WEDGED) > > return -EIO; > > if (*value & I915_RESET_IN_PROGRESS_FLAG) > > return -EAGAIN; > > return 0; > > } > = > Bleh, I've seen the light and this is overly complicated and doesn't > actually help make the code more readable than > = > if (intel_crtc->reset_counter !=3D atomic_read(&dev_priv->gpu_error.reset= _counter)) > return true; > = > The original patch is > Reviewed-by: Chris Wilson Thanks. I think we need cc:stable on this now. -- = Ville Syrj=E4l=E4 Intel OTC