Re: [PATCH v2] drm/i915/skl: Implement the skl version of MMIO flips

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Oct 28, 2014 at 10:57:45AM +0000, Damien Lespiau wrote:
> Because the plane registers are different in Skylake we need to adapt
> the MMIO code as well.
> 
> v2: Don't introduce yet another vfunc when the direction is do
> consolidate the plane updates to use the same code path (Daniel)
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 39 +++++++++++++++++++++++++++++++++++-
>  1 file changed, 38 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6d35484..bf65181 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9252,7 +9252,29 @@ static bool use_mmio_flip(struct intel_engine_cs *ring,
>  		return ring != obj->ring;
>  }
>  
> -static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
> +static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
> +{
> +       struct drm_device *dev = intel_crtc->base.dev;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       struct intel_framebuffer *intel_fb =
> +               to_intel_framebuffer(intel_crtc->base.primary->fb);
> +       struct drm_i915_gem_object *obj = intel_fb->obj;
> +       const int pipe = intel_crtc->pipe;

enum pipe

> +       u32 val;
> +
> +       val = I915_READ(PLANE_CTL(pipe, 0));
> +
> +       val &= ~PLANE_CTL_TILED_MASK;
> +       if (obj->tiling_mode == I915_TILING_X)
> +               val |= PLANE_CTL_TILED_X;

Hmm. Looks like you'd need to update PLANE_STRIDE too since it gets
computed differently for linear vs. tiled. PLANE_STRIDE does belong to
the set of registers armed by PLANE_SURF write so it should still be
atomic w/o any extra tricks.

> +
> +       I915_WRITE(PLANE_CTL(pipe, 0), val);
> +
> +       I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
> +       POSTING_READ(PLANE_SURF(pipe, 0));
> +}
> +
> +static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
>  {
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -9279,6 +9301,21 @@ static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
>  	POSTING_READ(DSPSURF(intel_crtc->plane));
>  }
>  
> +/*
> + * XXX: This is the temporary way to update the plane registers until we get
> + * around to using the usual plane update functions for MMIO flips
> + */
> +static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
> +{
> +	struct drm_device *dev = intel_crtc->base.dev;
> +
> +	if (INTEL_INFO(dev)->gen >= 9)
> +		skl_do_mmio_flip(intel_crtc);
> +	else
> +		/* use_mmio_flip() retricts MMIO flips to ilk+ */
> +		ilk_do_mmio_flip(intel_crtc);
> +}
> +
>  static int intel_postpone_flip(struct drm_i915_gem_object *obj)
>  {
>  	struct intel_engine_cs *ring;
> -- 
> 1.8.3.1
> 
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-- 
Ville Syrjälä
Intel OTC
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