[PATCH 1/2] drm/i915/chv: Add few more CHV workarounds

[PATCH 1/2] drm/i915/chv: Add few more CHV workarounds

[Arun Siluvery]

WaDisableInstructionShootdown:chv
WaForceEnableNonCoherent:chv
WaHdcDisableFetchWhenMasked:chv
WaDisableFenceDestinationToSLM:chv (pre-production)

s/WaDisableDopClockGating/WaDisableRowChickenDopClockGating, because another
CHV WA is defined with the same name in intel_pm.c for a different reg.

For: VIZ-4090
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77fce96..840e5d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5024,6 +5024,7 @@ enum punit_power_well {
 /* GEN8 chicken */
 #define HDC_CHICKEN0				0x7300
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 
 /* WaCatErrorRejectionIssue */
@@ -5941,6 +5942,7 @@ enum punit_power_well {
 #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
 
 #define GEN8_ROW_CHICKEN		0xe4f0
+#define   INSTRUCTION_SHOOTDOWN_DISABLE (1<<9)
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
 #define   STALL_DOP_GATING_DISABLE		(1<<5)
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a8f72e8..2c07a02 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -788,14 +788,30 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	/* WaDisablePartialInstShootdown:chv */
+	/* WaDisableInstructionShootdown:chv */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
-		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
+			  (dev->pdev->revision < 0x06 ?
+			   INSTRUCTION_SHOOTDOWN_DISABLE : 0));
 
 	/* WaDisableThreadStallDopClockGating:chv */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 		  STALL_DOP_GATING_DISABLE);
 
-	/* WaDisableDopClockGating:chv (pre-production hw) */
+	/* Use Force Non-Coherent whenever executing a 3D context. This is a
+	 * workaround for a possible hang in the unlikely event a TLB
+	 * invalidation occurs during a PSD flush.
+	 */
+	/* WaForceEnableNonCoherent:chv */
+	/* WaHdcDisableFetchWhenMasked:chv */
+	/* WaDisableFenceDestinationToSLM:chv (pre-production) */
+	WA_SET_BIT_MASKED(HDC_CHICKEN0,
+			  HDC_FORCE_NON_COHERENT |
+			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
+			  (dev->pdev->revision < 0x06 ?
+			   HDC_FENCE_DEST_SLM_DISABLE : 0));
+
+	/* WaDisableRowChickenDopClockGating:chv (pre-production hw) */
 	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 		  DOP_CLOCK_GATING_DISABLE);
 
-- 
2.1.2

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[PATCH 2/2] drm/i915/gen8: Apply pre-production WA based on revision

[Arun Siluvery]

Some of the workarounds are not required to be applied in later
revisions so restrict them based on revision.

For: VIZ-4090
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++++--------
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 059330c..b80d7ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2107,6 +2107,8 @@ struct drm_i915_cmd_table {
 				 ((INTEL_DEVID(dev) & 0xf) == 0x2  || \
 				 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
 				 (INTEL_DEVID(dev) & 0xf) == 0xe))
+#define IS_BDW_GT2(dev)		(IS_BROADWELL(dev) && \
+				 (INTEL_DEVID(dev) & 0x00F0) == 0x0010)
 #define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
 #define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2c07a02..e527c74 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -746,7 +746,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
 	/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
-			  STALL_DOP_GATING_DISABLE);
+			  (IS_BDW_GT2(dev) && dev->pdev->revision < 0x06) ?
+			  STALL_DOP_GATING_DISABLE : 0);
 
 	/* WaDisableDopClockGating:bdw */
 	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
@@ -756,13 +757,16 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
 			  GEN8_SAMPLER_POWER_BYPASS_DIS);
 
 	/* Use Force Non-Coherent whenever executing a 3D context. This is a
-	 * workaround for for a possible hang in the unlikely event a TLB
+	 * workaround for a possible hang in the unlikely event a TLB
 	 * invalidation occurs during a PSD flush.
 	 */
 	/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0,
 			  HDC_FORCE_NON_COHERENT |
-			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
+			  ((IS_BDW_GT3(dev) &&
+			    (dev->pdev->revision == 0x08 ||
+			     dev->pdev->revision == 0x09))
+			   ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 
 	/* Wa4x4STCOptimizationDisable:bdw */
 	WA_SET_BIT_MASKED(CACHE_MODE_1,
@@ -812,12 +816,12 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
 			   HDC_FENCE_DEST_SLM_DISABLE : 0));
 
 	/* WaDisableRowChickenDopClockGating:chv (pre-production hw) */
-	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
-		  DOP_CLOCK_GATING_DISABLE);
-
 	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
-	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
-		  GEN8_SAMPLER_POWER_BYPASS_DIS);
+	if (dev->pdev->revision < 0x06) {
+		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, DOP_CLOCK_GATING_DISABLE);
+		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
+				  GEN8_SAMPLER_POWER_BYPASS_DIS);
+	}
 
 	return 0;
 }
-- 
2.1.2

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Re: [PATCH 1/2] drm/i915/chv: Add few more CHV workarounds

[Ville Syrjälä]

On Tue, Oct 28, 2014 at 11:57:50AM +0000, Arun Siluvery wrote:
> WaDisableInstructionShootdown:chv
> WaForceEnableNonCoherent:chv
> WaHdcDisableFetchWhenMasked:chv
> WaDisableFenceDestinationToSLM:chv (pre-production)
> 
> s/WaDisableDopClockGating/WaDisableRowChickenDopClockGating, because another
> CHV WA is defined with the same name in intel_pm.c for a different reg.
> 
> For: VIZ-4090
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |  2 ++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++++++++++--
>  2 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 77fce96..840e5d9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5024,6 +5024,7 @@ enum punit_power_well {
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				0x7300
>  #define  HDC_FORCE_NON_COHERENT			(1<<4)
> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>  #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>  
>  /* WaCatErrorRejectionIssue */
> @@ -5941,6 +5942,7 @@ enum punit_power_well {
>  #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
>  
>  #define GEN8_ROW_CHICKEN		0xe4f0
> +#define   INSTRUCTION_SHOOTDOWN_DISABLE (1<<9)
>  #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
>  #define   STALL_DOP_GATING_DISABLE		(1<<5)
>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a8f72e8..2c07a02 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -788,14 +788,30 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	/* WaDisablePartialInstShootdown:chv */
> +	/* WaDisableInstructionShootdown:chv */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> -		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
> +			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> +			  (dev->pdev->revision < 0x06 ?
> +			   INSTRUCTION_SHOOTDOWN_DISABLE : 0));

I think we should just drop the current early pre-prod workarounds, and
not add more of them.

>  
>  	/* WaDisableThreadStallDopClockGating:chv */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  		  STALL_DOP_GATING_DISABLE);
>  
> -	/* WaDisableDopClockGating:chv (pre-production hw) */
> +	/* Use Force Non-Coherent whenever executing a 3D context. This is a
> +	 * workaround for a possible hang in the unlikely event a TLB
> +	 * invalidation occurs during a PSD flush.
> +	 */

We haven't generally documented the w/as in any great detail. Does it
help someone if we start doing that?

> +	/* WaForceEnableNonCoherent:chv */
> +	/* WaHdcDisableFetchWhenMasked:chv */
> +	/* WaDisableFenceDestinationToSLM:chv (pre-production) */
> +	WA_SET_BIT_MASKED(HDC_CHICKEN0,
> +			  HDC_FORCE_NON_COHERENT |
> +			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> +			  (dev->pdev->revision < 0x06 ?
> +			   HDC_FENCE_DEST_SLM_DISABLE : 0));
> +
> +	/* WaDisableRowChickenDopClockGating:chv (pre-production hw) */
>  	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>  		  DOP_CLOCK_GATING_DISABLE);
>  
> -- 
> 2.1.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 1/2] drm/i915/chv: Add few more CHV workarounds

[Siluvery, Arun]

On 28/10/2014 12:23, Ville Syrjälä wrote:
> On Tue, Oct 28, 2014 at 11:57:50AM +0000, Arun Siluvery wrote:
>> WaDisableInstructionShootdown:chv
>> WaForceEnableNonCoherent:chv
>> WaHdcDisableFetchWhenMasked:chv
>> WaDisableFenceDestinationToSLM:chv (pre-production)
>>
>> s/WaDisableDopClockGating/WaDisableRowChickenDopClockGating, because another
>> CHV WA is defined with the same name in intel_pm.c for a different reg.
>>
>> For: VIZ-4090
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h         |  2 ++
>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++++++++++--
>>   2 files changed, 20 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 77fce96..840e5d9 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5024,6 +5024,7 @@ enum punit_power_well {
>>   /* GEN8 chicken */
>>   #define HDC_CHICKEN0				0x7300
>>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
>> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>>
>>   /* WaCatErrorRejectionIssue */
>> @@ -5941,6 +5942,7 @@ enum punit_power_well {
>>   #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
>>
>>   #define GEN8_ROW_CHICKEN		0xe4f0
>> +#define   INSTRUCTION_SHOOTDOWN_DISABLE (1<<9)
>>   #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
>>   #define   STALL_DOP_GATING_DISABLE		(1<<5)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index a8f72e8..2c07a02 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -788,14 +788,30 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>
>>   	/* WaDisablePartialInstShootdown:chv */
>> +	/* WaDisableInstructionShootdown:chv */
>>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> -		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>> +			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
>> +			  (dev->pdev->revision < 0x06 ?
>> +			   INSTRUCTION_SHOOTDOWN_DISABLE : 0));
>
> I think we should just drop the current early pre-prod workarounds, and
> not add more of them.
>
ok I will drop this.
Is there any guideline on particular revision for bdw, chv below which 
we should drop that workaround?

>>
>>   	/* WaDisableThreadStallDopClockGating:chv */
>>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>>   		  STALL_DOP_GATING_DISABLE);
>>
>> -	/* WaDisableDopClockGating:chv (pre-production hw) */
>> +	/* Use Force Non-Coherent whenever executing a 3D context. This is a
>> +	 * workaround for a possible hang in the unlikely event a TLB
>> +	 * invalidation occurs during a PSD flush.
>> +	 */
>
> We haven't generally documented the w/as in any great detail. Does it
> help someone if we start doing that?

This was already documented for bdw hence I included it for chv also.

regards
Arun

>
>> +	/* WaForceEnableNonCoherent:chv */
>> +	/* WaHdcDisableFetchWhenMasked:chv */
>> +	/* WaDisableFenceDestinationToSLM:chv (pre-production) */
>> +	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>> +			  HDC_FORCE_NON_COHERENT |
>> +			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
>> +			  (dev->pdev->revision < 0x06 ?
>> +			   HDC_FENCE_DEST_SLM_DISABLE : 0));
>> +
>> +	/* WaDisableRowChickenDopClockGating:chv (pre-production hw) */
>>   	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>>   		  DOP_CLOCK_GATING_DISABLE);
>>
>> --
>> 2.1.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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Re: [PATCH 1/2] drm/i915/chv: Add few more CHV workarounds

[Ville Syrjälä]

On Tue, Oct 28, 2014 at 01:32:01PM +0000, Siluvery, Arun wrote:
> On 28/10/2014 12:23, Ville Syrjälä wrote:
> > On Tue, Oct 28, 2014 at 11:57:50AM +0000, Arun Siluvery wrote:
> >> WaDisableInstructionShootdown:chv
> >> WaForceEnableNonCoherent:chv
> >> WaHdcDisableFetchWhenMasked:chv
> >> WaDisableFenceDestinationToSLM:chv (pre-production)
> >>
> >> s/WaDisableDopClockGating/WaDisableRowChickenDopClockGating, because another
> >> CHV WA is defined with the same name in intel_pm.c for a different reg.
> >>
> >> For: VIZ-4090
> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_reg.h         |  2 ++
> >>   drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++++++++++--
> >>   2 files changed, 20 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 77fce96..840e5d9 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -5024,6 +5024,7 @@ enum punit_power_well {
> >>   /* GEN8 chicken */
> >>   #define HDC_CHICKEN0				0x7300
> >>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
> >> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
> >>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
> >>
> >>   /* WaCatErrorRejectionIssue */
> >> @@ -5941,6 +5942,7 @@ enum punit_power_well {
> >>   #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
> >>
> >>   #define GEN8_ROW_CHICKEN		0xe4f0
> >> +#define   INSTRUCTION_SHOOTDOWN_DISABLE (1<<9)
> >>   #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
> >>   #define   STALL_DOP_GATING_DISABLE		(1<<5)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> index a8f72e8..2c07a02 100644
> >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> @@ -788,14 +788,30 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> >>   	struct drm_i915_private *dev_priv = dev->dev_private;
> >>
> >>   	/* WaDisablePartialInstShootdown:chv */
> >> +	/* WaDisableInstructionShootdown:chv */
> >>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> >> -		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
> >> +			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> >> +			  (dev->pdev->revision < 0x06 ?
> >> +			   INSTRUCTION_SHOOTDOWN_DISABLE : 0));
> >
> > I think we should just drop the current early pre-prod workarounds, and
> > not add more of them.
> >
> ok I will drop this.
> Is there any guideline on particular revision for bdw, chv below which 
> we should drop that workaround?

The usual rule is to drop all pre-prod w/as once we know what actually
is the first production stepping. But obviosuly it's still a bit too
early to do that on chv. At this time I would just drop all A step ones.

> 
> >>
> >>   	/* WaDisableThreadStallDopClockGating:chv */
> >>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> >>   		  STALL_DOP_GATING_DISABLE);
> >>
> >> -	/* WaDisableDopClockGating:chv (pre-production hw) */
> >> +	/* Use Force Non-Coherent whenever executing a 3D context. This is a
> >> +	 * workaround for a possible hang in the unlikely event a TLB
> >> +	 * invalidation occurs during a PSD flush.
> >> +	 */
> >
> > We haven't generally documented the w/as in any great detail. Does it
> > help someone if we start doing that?
> 
> This was already documented for bdw hence I included it for chv also.

OK. Being a bit more consistent between bdw and chv shouldn't hurt.

> 
> regards
> Arun
> 
> >
> >> +	/* WaForceEnableNonCoherent:chv */
> >> +	/* WaHdcDisableFetchWhenMasked:chv */
> >> +	/* WaDisableFenceDestinationToSLM:chv (pre-production) */
> >> +	WA_SET_BIT_MASKED(HDC_CHICKEN0,
> >> +			  HDC_FORCE_NON_COHERENT |
> >> +			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> >> +			  (dev->pdev->revision < 0x06 ?
> >> +			   HDC_FENCE_DEST_SLM_DISABLE : 0));
> >> +
> >> +	/* WaDisableRowChickenDopClockGating:chv (pre-production hw) */
> >>   	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> >>   		  DOP_CLOCK_GATING_DISABLE);
> >>
> >> --
> >> 2.1.2
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 1/2] drm/i915/chv: Add few more CHV workarounds

[Jani Nikula]

On Tue, 28 Oct 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Oct 28, 2014 at 01:32:01PM +0000, Siluvery, Arun wrote:
>> On 28/10/2014 12:23, Ville Syrjälä wrote:
>> > On Tue, Oct 28, 2014 at 11:57:50AM +0000, Arun Siluvery wrote:
>> >> WaDisableInstructionShootdown:chv
>> >> WaForceEnableNonCoherent:chv
>> >> WaHdcDisableFetchWhenMasked:chv
>> >> WaDisableFenceDestinationToSLM:chv (pre-production)
>> >>
>> >> s/WaDisableDopClockGating/WaDisableRowChickenDopClockGating, because another
>> >> CHV WA is defined with the same name in intel_pm.c for a different reg.
>> >>
>> >> For: VIZ-4090
>> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> >> ---
>> >>   drivers/gpu/drm/i915/i915_reg.h         |  2 ++
>> >>   drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++++++++++--
>> >>   2 files changed, 20 insertions(+), 2 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> >> index 77fce96..840e5d9 100644
>> >> --- a/drivers/gpu/drm/i915/i915_reg.h
>> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> >> @@ -5024,6 +5024,7 @@ enum punit_power_well {
>> >>   /* GEN8 chicken */
>> >>   #define HDC_CHICKEN0				0x7300
>> >>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
>> >> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>> >>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>> >>
>> >>   /* WaCatErrorRejectionIssue */
>> >> @@ -5941,6 +5942,7 @@ enum punit_power_well {
>> >>   #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
>> >>
>> >>   #define GEN8_ROW_CHICKEN		0xe4f0
>> >> +#define   INSTRUCTION_SHOOTDOWN_DISABLE (1<<9)
>> >>   #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
>> >>   #define   STALL_DOP_GATING_DISABLE		(1<<5)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> >> index a8f72e8..2c07a02 100644
>> >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> >> @@ -788,14 +788,30 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>> >>   	struct drm_i915_private *dev_priv = dev->dev_private;
>> >>
>> >>   	/* WaDisablePartialInstShootdown:chv */
>> >> +	/* WaDisableInstructionShootdown:chv */
>> >>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> >> -		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>> >> +			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
>> >> +			  (dev->pdev->revision < 0x06 ?
>> >> +			   INSTRUCTION_SHOOTDOWN_DISABLE : 0));
>> >
>> > I think we should just drop the current early pre-prod workarounds, and
>> > not add more of them.
>> >
>> ok I will drop this.
>> Is there any guideline on particular revision for bdw, chv below which 
>> we should drop that workaround?
>
> The usual rule is to drop all pre-prod w/as once we know what actually
> is the first production stepping. But obviosuly it's still a bit too
> early to do that on chv. At this time I would just drop all A step ones.

Here's an idea.

Make all pre-prod workarounds conditional to i915.preliminary_hw_support.

Remove all pre-prod workarounds for a platform when that platform no
longer requires i915.preliminary_hw_support.

BR,
Jani.



-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH] drm/i915/chv: Add new WA and remove pre-production ones

[Arun Siluvery]

+WaForceEnableNonCoherent:chv
+WaHdcDisableFetchWhenMasked:chv
-WaDisableDopClockGating:chv
-WaDisableSamplerPowerBypass:chv
-WaDisableGunitClockGating:chv
-WaDisableFfDopClockGating:chv
-WaDisableDopClockGating:chv

WaDisablePartialInstShootdown:chv and
WaDisableThreadStallDopClockGating:chv are related to the
same register so combine them.

v2: Remove pre-production WA instead of restricting them
based on revision id (Ville)

For: VIZ-4090
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  1 +
 drivers/gpu/drm/i915/intel_pm.c         | 12 ------------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +++++++++++-----------
 3 files changed, 12 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77fce96..9d39700 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5024,6 +5024,7 @@ enum punit_power_well {
 /* GEN8 chicken */
 #define HDC_CHICKEN0				0x7300
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 
 /* WaCatErrorRejectionIssue */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7a69eba..93db25f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5944,18 +5944,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSDEUnitClockGating:chv */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
-	/* WaDisableGunitClockGating:chv (pre-production hw) */
-	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
-		   GINT_DIS);
-
-	/* WaDisableFfDopClockGating:chv (pre-production hw) */
-	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
-		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
-
-	/* WaDisableDopClockGating:chv (pre-production hw) */
-	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
-		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a8f72e8..368b20a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -788,20 +788,20 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	/* WaDisablePartialInstShootdown:chv */
-	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
-		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
-
 	/* WaDisableThreadStallDopClockGating:chv */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
-		  STALL_DOP_GATING_DISABLE);
-
-	/* WaDisableDopClockGating:chv (pre-production hw) */
-	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
-		  DOP_CLOCK_GATING_DISABLE);
+			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
+			  STALL_DOP_GATING_DISABLE);
 
-	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
-	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
-		  GEN8_SAMPLER_POWER_BYPASS_DIS);
+	/* Use Force Non-Coherent whenever executing a 3D context. This is a
+	 * workaround for a possible hang in the unlikely event a TLB
+	 * invalidation occurs during a PSD flush.
+	 */
+	/* WaForceEnableNonCoherent:chv */
+	/* WaHdcDisableFetchWhenMasked:chv */
+	WA_SET_BIT_MASKED(HDC_CHICKEN0,
+			  HDC_FORCE_NON_COHERENT |
+			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 
 	return 0;
 }
-- 
2.1.2

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Re: [PATCH] drm/i915/chv: Add new WA and remove pre-production ones

[Ville Syrjälä]

On Tue, Oct 28, 2014 at 03:48:24PM +0000, Arun Siluvery wrote:
> +WaForceEnableNonCoherent:chv
> +WaHdcDisableFetchWhenMasked:chv
> -WaDisableDopClockGating:chv
> -WaDisableSamplerPowerBypass:chv
> -WaDisableGunitClockGating:chv
> -WaDisableFfDopClockGating:chv
> -WaDisableDopClockGating:chv
> 
> WaDisablePartialInstShootdown:chv and
> WaDisableThreadStallDopClockGating:chv are related to the
> same register so combine them.

Please split into at least two patches (one to add new w/as and another to
remove old ones). Otherwise reverting is a pita in case we find that one
of the dropped w/as was actually still needed.

> 
> v2: Remove pre-production WA instead of restricting them
> based on revision id (Ville)
> 
> For: VIZ-4090
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |  1 +
>  drivers/gpu/drm/i915/intel_pm.c         | 12 ------------
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +++++++++++-----------
>  3 files changed, 12 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 77fce96..9d39700 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5024,6 +5024,7 @@ enum punit_power_well {
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				0x7300
>  #define  HDC_FORCE_NON_COHERENT			(1<<4)
> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>  #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>  
>  /* WaCatErrorRejectionIssue */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7a69eba..93db25f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5944,18 +5944,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>  	/* WaDisableSDEUnitClockGating:chv */
>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> -
> -	/* WaDisableGunitClockGating:chv (pre-production hw) */
> -	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
> -		   GINT_DIS);

OK

> -
> -	/* WaDisableFfDopClockGating:chv (pre-production hw) */
> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> -		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));

OK

> -
> -	/* WaDisableDopClockGating:chv (pre-production hw) */
> -	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> -		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);

OK, I think. This was the weird w/a where it seemed hard to figure out
what it needed. Nothing in BSpec about needing this bit on chv.

>  }
>  
>  static void g4x_init_clock_gating(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a8f72e8..368b20a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -788,20 +788,20 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	/* WaDisablePartialInstShootdown:chv */
> -	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> -		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
> -
>  	/* WaDisableThreadStallDopClockGating:chv */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> -		  STALL_DOP_GATING_DISABLE);
> -
> -	/* WaDisableDopClockGating:chv (pre-production hw) */
> -	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> -		  DOP_CLOCK_GATING_DISABLE);

OK, again the weird w/a but Bspec seems to agree at least.

> +			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> +			  STALL_DOP_GATING_DISABLE);

Bspec says bit 5 is MBZ now, and yet the w/a database says it's
forever. And the hardware accepts 1 there so it's not like many other
MBZ bits that you can't set even if you try. Also Bspec has three
different definitions for this bit on gen8, all disagree with each other
and one definiton even manages to disagree with itself. And reading the
hsd stuff I'm not the only that has been confused by this, and yet I see
no conclusion there as to how this bit should be configured.

Oh well, I guess we can leave it set for now and maybe eventually
someone will figure out what we're supposed to do.

>  
> -	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> -	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> -		  GEN8_SAMPLER_POWER_BYPASS_DIS);

OK

> +	/* Use Force Non-Coherent whenever executing a 3D context. This is a
> +	 * workaround for a possible hang in the unlikely event a TLB
> +	 * invalidation occurs during a PSD flush.
> +	 */
> +	/* WaForceEnableNonCoherent:chv */
> +	/* WaHdcDisableFetchWhenMasked:chv */
> +	WA_SET_BIT_MASKED(HDC_CHICKEN0,
> +			  HDC_FORCE_NON_COHERENT |
> +			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);

OK

Right, so split it up a bit and you can add

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

to the patches.

>  
>  	return 0;
>  }
> -- 
> 2.1.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915/chv: Add new WA and remove pre-production ones

[Siluvery, Arun]

On 28/10/2014 17:06, Ville Syrjälä wrote:
> On Tue, Oct 28, 2014 at 03:48:24PM +0000, Arun Siluvery wrote:
>> +WaForceEnableNonCoherent:chv
>> +WaHdcDisableFetchWhenMasked:chv
>> -WaDisableDopClockGating:chv
>> -WaDisableSamplerPowerBypass:chv
>> -WaDisableGunitClockGating:chv
>> -WaDisableFfDopClockGating:chv
>> -WaDisableDopClockGating:chv
>>
>> WaDisablePartialInstShootdown:chv and
>> WaDisableThreadStallDopClockGating:chv are related to the
>> same register so combine them.
>
> Please split into at least two patches (one to add new w/as and another to
> remove old ones). Otherwise reverting is a pita in case we find that one
> of the dropped w/as was actually still needed.
>

I thought of doing that but then combined them as these are early 
pre-production ones and we may not need them in future but I agree 
splitting them helps in reverting them if required.

>>
>> v2: Remove pre-production WA instead of restricting them
>> based on revision id (Ville)
>>
>> For: VIZ-4090
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h         |  1 +
>>   drivers/gpu/drm/i915/intel_pm.c         | 12 ------------
>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +++++++++++-----------
>>   3 files changed, 12 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 77fce96..9d39700 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5024,6 +5024,7 @@ enum punit_power_well {
>>   /* GEN8 chicken */
>>   #define HDC_CHICKEN0				0x7300
>>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
>> +#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>>
>>   /* WaCatErrorRejectionIssue */
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 7a69eba..93db25f 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -5944,18 +5944,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>>   	/* WaDisableSDEUnitClockGating:chv */
>>   	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>>   		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>> -
>> -	/* WaDisableGunitClockGating:chv (pre-production hw) */
>> -	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
>> -		   GINT_DIS);
>
> OK
>
>> -
>> -	/* WaDisableFfDopClockGating:chv (pre-production hw) */
>> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
>> -		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
>
> OK
>
>> -
>> -	/* WaDisableDopClockGating:chv (pre-production hw) */
>> -	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>> -		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>
> OK, I think. This was the weird w/a where it seemed hard to figure out
> what it needed. Nothing in BSpec about needing this bit on chv.
>
>>   }
>>
>>   static void g4x_init_clock_gating(struct drm_device *dev)
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index a8f72e8..368b20a 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -788,20 +788,20 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>
>>   	/* WaDisablePartialInstShootdown:chv */
>> -	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> -		  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>> -
>>   	/* WaDisableThreadStallDopClockGating:chv */
>>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> -		  STALL_DOP_GATING_DISABLE);
>> -
>> -	/* WaDisableDopClockGating:chv (pre-production hw) */
>> -	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>> -		  DOP_CLOCK_GATING_DISABLE);
>
> OK, again the weird w/a but Bspec seems to agree at least.
>
>> +			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
>> +			  STALL_DOP_GATING_DISABLE);
>
> Bspec says bit 5 is MBZ now, and yet the w/a database says it's
> forever. And the hardware accepts 1 there so it's not like many other
> MBZ bits that you can't set even if you try. Also Bspec has three
> different definitions for this bit on gen8, all disagree with each other
> and one definiton even manages to disagree with itself. And reading the
> hsd stuff I'm not the only that has been confused by this, and yet I see
> no conclusion there as to how this bit should be configured.
>
> Oh well, I guess we can leave it set for now and maybe eventually
> someone will figure out what we're supposed to do.
>
I am using w/a database as reference and it says forever, spec seems to 
disagree but probably not yet updated.

regards
Arun

>>
>> -	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
>> -	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>> -		  GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> OK
>
>> +	/* Use Force Non-Coherent whenever executing a 3D context. This is a
>> +	 * workaround for a possible hang in the unlikely event a TLB
>> +	 * invalidation occurs during a PSD flush.
>> +	 */
>> +	/* WaForceEnableNonCoherent:chv */
>> +	/* WaHdcDisableFetchWhenMasked:chv */
>> +	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>> +			  HDC_FORCE_NON_COHERENT |
>> +			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
>
> OK
>
> Right, so split it up a bit and you can add
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> to the patches.
>
>>
>>   	return 0;
>>   }
>> --
>> 2.1.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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