From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/dp: only use training pattern 3 on platforms that support it Date: Wed, 29 Oct 2014 13:09:12 +0200 Message-ID: <20141029110912.GH4284@intel.com> References: <1414573406-17071-1-git-send-email-jani.nikula@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1414573406-17071-1-git-send-email-jani.nikula@intel.com> Sender: stable-owner@vger.kernel.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, airlied@gmail.com, daniel@ffwll.ch, stable@vger.kernel.org, tprevite@gmail.com List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 29, 2014 at 11:03:26AM +0200, Jani Nikula wrote: > Ivybridge + 30" monitor prints a drm error on every modeset, since IV= B > doesn't support DP3 we should even bother trying to use it. >=20 > This regression has been introduced in >=20 > commit 06ea66b6bb445043dc25a9626254d5c130093199 > Author: Todd Previte > Date: Mon Jan 20 10:19:39 2014 -0700 >=20 > drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capa= ble > devices >=20 > Reported-by: Dave Airlie > Reference: http://mid.gmane.org/1414566170-9868-1-git-send-email-airl= ied@gmail.com > Cc: Todd Previte > Cc: stable@vger.kernel.org (3.15+) > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_dp.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/i= ntel_dp.c > index 82e47dafe293..47e9d71c14a3 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3945,9 +3945,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > } > } > =20 > - /* Training Pattern 3 support */ > + /* Training Pattern 3 support, both source and sink */ > if (intel_dp->dpcd[DP_DPCD_REV] >=3D 0x12 && > - intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { > + intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED && > + (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >=3D 8)) { Yep that looks better. Additonally we could drop the 'link_bw =3D=3D DP_LINK_BW_5_4' check from intel_dp_complete_link_train= () and just rely on use_tps3 since pattern 3 is mandatory for HBR2 capable sinks, and so they really should advertise DP_TPS3_SUPPORTED. But on the other hand I don't see any harm in keeping the current logic there. Reviewed-by: Ville Syrj=E4l=E4 > intel_dp->use_tps3 =3D true; > DRM_DEBUG_KMS("Displayport TPS3 supported\n"); > } else > --=20 > 2.1.1 --=20 Ville Syrj=E4l=E4 Intel OTC