Re: [PATCH 03/14] drm/i915: Use gen8_gt_irq_reset() in cherryview_irq_uninstall()

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Oct 30, 2014 at 04:49:21PM -0200, Paulo Zanoni wrote:
> 2014-10-30 15:42 GMT-02:00  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Replace the hand rolled macros with gen8_gt_irq_reset() and
> > GEN5_IRQ_RESET() in cherryview_irq_uninstall().
> >
> 
> I guess that was the result of a rebase?

I originally mostly copy pasted these from the bdw code, and then while
chv was sitting in an internal tree the big irq cleanup(s) happened.
But the chv code kept working even if upstream changed so there was no
major urgency to change it.

> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 28 ++--------------------------
> >  1 file changed, 2 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index e41272d..1ec4ebb 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3625,33 +3625,9 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
> >         I915_WRITE(GEN8_MASTER_IRQ, 0);
> >         POSTING_READ(GEN8_MASTER_IRQ);
> >
> > -#define GEN8_IRQ_FINI_NDX(type, which)                         \
> > -do {                                                           \
> > -       I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);       \
> > -       I915_WRITE(GEN8_##type##_IER(which), 0);                \
> > -       I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);       \
> > -       POSTING_READ(GEN8_##type##_IIR(which));                 \
> > -       I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);       \
> > -} while (0)
> > -
> > -#define GEN8_IRQ_FINI(type)                            \
> > -do {                                                   \
> > -       I915_WRITE(GEN8_##type##_IMR, 0xffffffff);      \
> > -       I915_WRITE(GEN8_##type##_IER, 0);               \
> > -       I915_WRITE(GEN8_##type##_IIR, 0xffffffff);      \
> > -       POSTING_READ(GEN8_##type##_IIR);                \
> > -       I915_WRITE(GEN8_##type##_IIR, 0xffffffff);      \
> > -} while (0)
> > -
> > -       GEN8_IRQ_FINI_NDX(GT, 0);
> > -       GEN8_IRQ_FINI_NDX(GT, 1);
> > -       GEN8_IRQ_FINI_NDX(GT, 2);
> > -       GEN8_IRQ_FINI_NDX(GT, 3);
> > -
> > -       GEN8_IRQ_FINI(PCU);
> > +       gen8_gt_irq_reset(dev_priv);
> >
> > -#undef GEN8_IRQ_FINI
> > -#undef GEN8_IRQ_FINI_NDX
> > +       GEN5_IRQ_RESET(GEN8_PCU_);
> >
> >         I915_WRITE(PORT_HOTPLUG_EN, 0);
> >         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> > --
> > 2.0.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC
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