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From: Daniel Vetter <daniel@ffwll.ch>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases
Date: Mon, 3 Nov 2014 12:10:17 +0100	[thread overview]
Message-ID: <20141103111017.GK26941@phenom.ffwll.local> (raw)
In-Reply-To: <20141028181230.GB4284@intel.com>

On Tue, Oct 28, 2014 at 08:12:30PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 28, 2014 at 10:57:38AM -0700, Jesse Barnes wrote:
> > On Thu, 16 Oct 2014 20:52:33 +0300
> > ville.syrjala@linux.intel.com wrote:
> > 
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > In case the cmnlane power well is down but cmnreset isn't asserted we
> > > would currently skip the off+on toggle for the power well. That could
> > > leave cmnreset deasserted while cmnlane is powered down which might
> > > lead to problems with the PHY.
> > > 
> > > To avoid such issues skip the cmnlane toggle only if both cmnlane and
> > > disp2d wells are up and cmnreset is already deasserted. In all other
> > > cases power down the cmnlane well which will also make sure cmnreset
> > > gets asserted correctly while cmnlane is powered down.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++-----
> > >  1 file changed, 2 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c index 36749b9..f6b4e8d
> > > 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -1137,12 +1137,9 @@ static void vlv_cmnlane_wa(struct
> > > drm_i915_private *dev_priv) struct i915_power_well *disp2d =
> > >  		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
> > >  
> > > -	/* nothing to do if common lane is already off */
> > > -	if (!cmn->ops->is_enabled(dev_priv, cmn))
> > > -		return;
> > > -
> > >  	/* If the display might be already active skip this */
> > > -	if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
> > > +	if (cmn->ops->is_enabled(dev_priv, cmn) &&
> > > +	    disp2d->ops->is_enabled(dev_priv, disp2d) &&
> > >  	    I915_READ(DPIO_CTL) & DPIO_CMNRST)
> > >  		return;
> > >  
> > 
> > 
> > Yeah looks ok.  Do we have any bugs we know this fixes?
> 
> Not sure. I don't really know if I ever saw a machine that really
> needed this toggling. But I did simulate crappy BIOS for it once by
> turning on the cmn well but leaving everything else off, and after the
> toggle w/a nothing got stuck so it seemed to do the right thing at least :)
> 
> > I'm hoping the
> > remaining VLV DP training failures are fixed either by something like
> > this or your panel power sequencer fixes.
> 
> Me too. I think it should be pretty solid after those. Then we just need
> to figure out how to make it fast again if it really got much slower.
> But at least the massive init time increase might be fixed by the
> timestamp init patch I posted today.
> 
> > 
> > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Remaining two patches merged to dinq - we can always cherry-pick to -fixes
if this resolves a real issue.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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  reply	other threads:[~2014-11-03 11:10 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-16 17:52 [PATCH 0/5] drm/i915: Random pile of VLV/CHV fixes ville.syrjala
2014-10-16 17:52 ` [PATCH 1/5] drm/i915: Don't claim that we're resetting PCH ADPA register ville.syrjala
2014-10-17  8:50   ` Jani Nikula
2014-10-16 17:52 ` [PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv ville.syrjala
2014-10-17  8:59   ` Jani Nikula
2014-10-17  9:00   ` Jani Nikula
2014-10-22 13:41     ` Jani Nikula
2014-10-16 17:52 ` [PATCH 3/5] drm/i915: Fix chv PCS DW11 register defines ville.syrjala
2014-10-17  9:08   ` Jani Nikula
2014-10-21 16:08     ` Daniel Vetter
2014-10-16 17:52 ` [PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases ville.syrjala
2014-10-28 17:57   ` Jesse Barnes
2014-10-28 18:12     ` Ville Syrjälä
2014-11-03 11:10       ` Daniel Vetter [this message]
2014-10-16 17:52 ` [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers ville.syrjala
2014-10-29 21:18   ` Rodrigo Vivi
2014-10-30  8:33     ` Ville Syrjälä
2014-10-30 19:14       ` Rodrigo Vivi

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