[PATCH] drm/i915: Enable pipe-a power well on chv

[PATCH] drm/i915: Enable pipe-a power well on chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

It seems that the pipe-a power well has replaced the disp2d power well
on chv. At least that's the case with the current punit firmware. So
enable the pipe-a power and expand its domains to cover everything the
disp2d well ought to cover.

The other power wells (apart from the cmnlane wells) still seem awol
in the current punit firmware. So leave them disabled in the code.

This fixes a hilarious oops during resume on bsw where
intel_hdmi_get_config() would read the port register and get back
0xffffffff and thus think the port is enabled on pipe D. It would then
go and index the pipe_to_crtc_mapping[] array with PIPE_D and blow up
when intel_hdmi_get_config() tries to write to crtc->config. Someone
really ought to replace all naked pipe_to_crtc_mapping[] uses with the
appropriate function call so we could add a warning there if the pipe
doesn't actually exist...

We must also call the power seqeuencer state reset function from
the pipe-a well disable just like we do from disp2d on vlv. Otherwise
the eDP panel won't recover at resume time since the PPS has lost its
hold on the port.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84903
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
Note that this depends on my earlier power sequencer series.

 drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a44046f..fdf68a1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -629,6 +629,9 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
 		     power_well->data != PIPE_C);
 
 	chv_set_pipe_power_well(dev_priv, power_well, false);
+
+	if (power_well->data == PIPE_A)
+		vlv_power_sequencer_reset(dev_priv);
 }
 
 static void check_power_well_state(struct drm_i915_private *dev_priv,
@@ -980,12 +983,20 @@ static struct i915_power_well chv_power_wells[] = {
 		.data = PUNIT_POWER_WELL_DISP2D,
 		.ops = &vlv_display_power_well_ops,
 	},
+#endif
 	{
 		.name = "pipe-a",
-		.domains = CHV_PIPE_A_POWER_DOMAINS,
+		/*
+		 * FIXME: pipe A power well seems to be the new disp2d well.
+		 * At least all registers seem to be housed there. Figure
+		 * out if this a a temporary situation in pre-production
+		 * hardware or a permanent state of affairs.
+		 */
+		.domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS,
 		.data = PIPE_A,
 		.ops = &chv_pipe_power_well_ops,
 	},
+#if 0
 	{
 		.name = "pipe-b",
 		.domains = CHV_PIPE_B_POWER_DOMAINS,
-- 
2.0.4

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Re: [PATCH] drm/i915: Enable pipe-a power well on chv

[Jesse Barnes]

On Mon, 27 Oct 2014 16:07:32 +0200
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> It seems that the pipe-a power well has replaced the disp2d power well
> on chv. At least that's the case with the current punit firmware. So
> enable the pipe-a power and expand its domains to cover everything the
> disp2d well ought to cover.
> 
> The other power wells (apart from the cmnlane wells) still seem awol
> in the current punit firmware. So leave them disabled in the code.
> 
> This fixes a hilarious oops during resume on bsw where
> intel_hdmi_get_config() would read the port register and get back
> 0xffffffff and thus think the port is enabled on pipe D. It would then
> go and index the pipe_to_crtc_mapping[] array with PIPE_D and blow up
> when intel_hdmi_get_config() tries to write to crtc->config. Someone
> really ought to replace all naked pipe_to_crtc_mapping[] uses with the
> appropriate function call so we could add a warning there if the pipe
> doesn't actually exist...
> 
> We must also call the power seqeuencer state reset function from
> the pipe-a well disable just like we do from disp2d on vlv. Otherwise
> the eDP panel won't recover at resume time since the PPS has lost its
> hold on the port.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84903
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> Note that this depends on my earlier power sequencer series.
> 
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c index a44046f..fdf68a1
> 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -629,6 +629,9 @@ static void chv_pipe_power_well_disable(struct
> drm_i915_private *dev_priv, power_well->data != PIPE_C);
>  
>  	chv_set_pipe_power_well(dev_priv, power_well, false);
> +
> +	if (power_well->data == PIPE_A)
> +		vlv_power_sequencer_reset(dev_priv);
>  }
>  
>  static void check_power_well_state(struct drm_i915_private *dev_priv,
> @@ -980,12 +983,20 @@ static struct i915_power_well chv_power_wells[]
> = { .data = PUNIT_POWER_WELL_DISP2D,
>  		.ops = &vlv_display_power_well_ops,
>  	},
> +#endif
>  	{
>  		.name = "pipe-a",
> -		.domains = CHV_PIPE_A_POWER_DOMAINS,
> +		/*
> +		 * FIXME: pipe A power well seems to be the new
> disp2d well.
> +		 * At least all registers seem to be housed there.
> Figure
> +		 * out if this a a temporary situation in
> pre-production
> +		 * hardware or a permanent state of affairs.
> +		 */
> +		.domains = CHV_PIPE_A_POWER_DOMAINS |
> VLV_DISPLAY_POWER_DOMAINS, .data = PIPE_A,
>  		.ops = &chv_pipe_power_well_ops,
>  	},
> +#if 0
>  	{
>  		.name = "pipe-b",
>  		.domains = CHV_PIPE_B_POWER_DOMAINS,

Moar power wells.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH] drm/i915: Enable pipe-a power well on chv

[Daniel Vetter]

On Tue, Oct 28, 2014 at 10:59:05AM -0700, Jesse Barnes wrote:
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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