From: Daniel Vetter <daniel@ffwll.ch>
To: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com,
shuang.he@linux.intel.com
Subject: Re: [PATCH 4/9] drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs
Date: Mon, 3 Nov 2014 14:51:27 +0100 [thread overview]
Message-ID: <20141103135127.GF26941@phenom.ffwll.local> (raw)
In-Reply-To: <1414575158-28148-5-git-send-email-ander.conselvan.de.oliveira@intel.com>
On Wed, Oct 29, 2014 at 11:32:33AM +0200, Ander Conselvan de Oliveira wrote:
> It is possible for a mode set to fail if there aren't shared DPLLS that
> match the new configuration requirement or other errors in clock
> computation. If that step is executed after disabling crtcs, in the
> failure case the hardware configuration is changed and needs to be
> restored. Doing those things early will allow the mode set to fail
> before actually touching the hardware.
>
> Follow up patches will convert different platforms to use the new
> infrastructure.
>
> v2: Keep pll->new_config valid only during mode set (Ville)
> Use kmemdup() in i915_shared_dpll_start_config() (Ville)
> Restore old pll config if something fails before commit (Ville)
> Don't set compute_clock hooks since dev_priv is kzalloc()'d (Ville)
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Ran into a blocking question with this one, merged thus far.
> @@ -7395,6 +7456,9 @@ static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
> else
> crtc->new_config->dpll_hw_state.fp1 = fp;
>
> + if (intel_crtc_to_shared_dpll(crtc))
> + intel_put_shared_dpll(crtc);
Don't we need the same fixup in intel_ddi_pll_select?
> +
> pll = intel_get_shared_dpll(crtc);
> if (pll == NULL) {
> DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
> @@ -10739,6 +10803,22 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> prepare_pipes &= ~disable_pipes;
> }
>
> + if (dev_priv->display.crtc_compute_clock) {
> + unsigned clear_pipes = modeset_pipes | disable_pipes;
> +
> + ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
> + if (ret)
> + goto done;
> +
> + for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
> + ret = dev_priv->display.crtc_compute_clock(intel_crtc);
> + if (ret) {
> + intel_shared_dpll_abort_config(dev_priv);
> + goto done;
> + }
> + }
> + }
Might be useful to shuffle this and the vlv-specific code above into a new
intel_compute_global_config kind of helper function. But that can be done
later on I think.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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next prev parent reply other threads:[~2014-11-03 13:51 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-29 9:32 [PATCH v2 0/9] Stage shared dpll config Ander Conselvan de Oliveira
2014-10-29 9:32 ` [PATCH 1/9] drm/i915: Make *_crtc_mode_set work on new_config Ander Conselvan de Oliveira
2014-11-03 13:45 ` Daniel Vetter
2014-10-29 9:32 ` [PATCH 2/9] drm/i915: Convert shared dpll reference count to a crtc mask Ander Conselvan de Oliveira
2014-10-29 9:32 ` [PATCH 3/9] drm/i915: Move dpll crtc_mask and hw_state fields into separate struct Ander Conselvan de Oliveira
2014-10-29 9:32 ` [PATCH 4/9] drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs Ander Conselvan de Oliveira
2014-11-03 13:51 ` Daniel Vetter [this message]
2014-11-03 13:56 ` Daniel Vetter
2014-11-04 6:57 ` Ander Conselvan de Oliveira
2014-10-29 9:32 ` [PATCH 5/9] drm/i915: Covert HSW+ to choose DPLLS before disabling CRTCs Ander Conselvan de Oliveira
2014-10-29 9:32 ` [PATCH 6/9] drm/i915: Covert ILK-IVB " Ander Conselvan de Oliveira
2014-10-29 9:32 ` [PATCH 7/9] drm/i915: Covert remaining platforms " Ander Conselvan de Oliveira
2014-10-29 9:32 ` [PATCH 8/9] drm/i915: Remove crtc_mode_set() hook Ander Conselvan de Oliveira
2014-10-29 9:32 ` [PATCH 9/9] drm/i915: Don't store current shared DPLL in the new pipe_config Ander Conselvan de Oliveira
2014-10-29 13:56 ` [PATCH 9/9] drm/i915: Don't store current shared DPLL shuang.he
2014-11-03 14:09 ` [PATCH v2 0/9] Stage shared dpll config Daniel Vetter
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