From: Daniel Vetter <daniel@ffwll.ch>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 08/14] drm/i915: Make valleyview_display_irqs_(un)install() work for chv
Date: Mon, 3 Nov 2014 17:32:45 +0100 [thread overview]
Message-ID: <20141103163245.GG26941@phenom.ffwll.local> (raw)
In-Reply-To: <20141031094036.GB10649@intel.com>
On Fri, Oct 31, 2014 at 11:40:36AM +0200, Ville Syrjälä wrote:
> On Thu, Oct 30, 2014 at 06:12:51PM -0200, Paulo Zanoni wrote:
> > While trying to check for the correctness of the lines above, I
> > noticed that in __i915_enable_pipestat(), if the enable mask is
> > already what we want, we won't clear/update the status bits. Is that
> > correct? Why? Anyway, any problems in that function should be fixed by
> > a separate patch.
>
> I think the current behaviour is correct. We don't want to lose
> interrupts in case someone enables the same pipestat bit twice. But
> obviously then disabling twice doesn't work because we don't refcount
> the individual bits. So perhaps we want to print a warning if some of
> the bits we're trying to set are already set?
Yeah a warning in case something is disabled/enabled already might be
useful. That's valid for all the various irq mask handling helpers we have
in general though (i.e. gt, display ...).
And I'm pretty sure it'll lead to a massive WARN backtrace fest ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-11-03 16:32 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-30 17:42 [PATCH 00/14] drm/i915: IRQ work for chv mostly ville.syrjala
2014-10-30 17:42 ` [PATCH 01/14] drm/i915: Apply some ocd for IMR vs. IER order during irq enable ville.syrjala
2014-10-30 18:37 ` Paulo Zanoni
2014-10-30 17:42 ` [PATCH 02/14] drm/i915: Use DPINVGTT_STATUS_MASK ville.syrjala
2014-10-30 18:41 ` Paulo Zanoni
2014-10-30 19:15 ` Ville Syrjälä
2014-10-30 17:42 ` [PATCH 03/14] drm/i915: Use gen8_gt_irq_reset() in cherryview_irq_uninstall() ville.syrjala
2014-10-30 18:49 ` Paulo Zanoni
2014-10-30 19:20 ` Ville Syrjälä
2014-10-30 17:42 ` [PATCH 04/14] drm/i915: Drop the extra GEN8_PCU_IIR posting read from cherryview_irq_preinstall() ville.syrjala
2014-10-30 18:51 ` Paulo Zanoni
2014-10-30 17:42 ` [PATCH 05/14] drm/i915: Use a consistent order between IIR, IER, IMR writes on vlv/chv ville.syrjala
2014-10-30 19:24 ` Paulo Zanoni
2014-10-30 19:39 ` Ville Syrjälä
2014-10-30 17:42 ` [PATCH 06/14] drm/i915: Use GEN5_IRQ_RESET() " ville.syrjala
2014-10-30 19:37 ` Paulo Zanoni
2014-10-30 17:42 ` [PATCH 07/14] drm/i915: Call gen5_gt_irq_reset() from valleyview_irq_uninstall() ville.syrjala
2014-10-30 19:51 ` Paulo Zanoni
2014-10-31 9:35 ` Ville Syrjälä
2014-10-31 9:48 ` Ville Syrjälä
2014-11-03 16:30 ` Daniel Vetter
2014-10-30 17:42 ` [PATCH 08/14] drm/i915: Make valleyview_display_irqs_(un)install() work for chv ville.syrjala
2014-10-30 20:12 ` Paulo Zanoni
2014-10-31 9:40 ` Ville Syrjälä
2014-11-03 16:32 ` Daniel Vetter [this message]
2014-10-30 17:42 ` [PATCH 09/14] drm/i915: Refactor vlv_display_irq_reset() ville.syrjala
2014-10-30 20:19 ` Paulo Zanoni
2014-10-30 17:42 ` [PATCH 10/14] drm/i915: Refactor vlv_display_irq_uninstall() ville.syrjala
2014-10-30 20:22 ` Paulo Zanoni
2014-10-30 20:37 ` Paulo Zanoni
2014-10-31 9:43 ` Ville Syrjälä
2014-10-30 17:43 ` [PATCH 11/14] drm/i914: Refactor vlv_display_irq_postinstall() ville.syrjala
2014-10-30 20:25 ` Paulo Zanoni
2014-10-30 17:43 ` [PATCH 12/14] drm/i915: Drop useless VLV_IIR writes from vlv_display_irq_postinstall() ville.syrjala
2014-10-30 20:28 ` Paulo Zanoni
2014-10-30 17:43 ` [PATCH 13/14] drm/i915: Use vlv display irq setup code for chv ville.syrjala
2014-10-30 20:41 ` Paulo Zanoni
2014-10-31 10:04 ` Ville Syrjälä
2014-11-14 17:38 ` Paulo Zanoni
2014-11-03 16:37 ` Daniel Vetter
2014-10-30 17:43 ` [PATCH 14/14] drm/i915: Reinit display irqs and hpd from chv pipe-a power well ville.syrjala
2014-11-14 17:49 ` Paulo Zanoni
2014-11-14 18:45 ` Ville Syrjälä
2014-11-17 8:17 ` Daniel Vetter
2014-10-31 9:53 ` [PATCH 15/14] drm/i915: Kill leftover GTIIR writes from valleyview_irq_preinstall() ville.syrjala
2014-11-03 16:38 ` [PATCH 00/14] drm/i915: IRQ work for chv mostly Daniel Vetter
2014-11-04 12:21 ` Ville Syrjälä
2014-11-04 12:40 ` Daniel Vetter
2014-11-04 16:42 ` Ville Syrjälä
2014-11-05 9:29 ` Daniel Vetter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20141103163245.GG26941@phenom.ffwll.local \
--to=daniel@ffwll.ch \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox