From: "O'Rourke, Tom" <Tom.O'Rourke@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 03/10] drm/i915/chv: Use timeout mode for RC6 on chv
Date: Tue, 4 Nov 2014 14:36:15 -0800 [thread overview]
Message-ID: <20141104223615.GA63758@torourke-desk1> (raw)
In-Reply-To: <1415105508-1590-4-git-send-email-rodrigo.vivi@intel.com>
On Tue, Nov 04, 2014 at 04:51:41AM -0800, Rodrigo Vivi wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> Higher RC6 residency is observed using timeout mode
> instead of EI mode. It's Recommended to use TO Method for RC6.
>
[TOR:] My comments on the previous version of this patch are at
http://lists.freedesktop.org/archives/intel-gfx/2014-August/050203.html
Based on the understanding this patch will provide benefit
on some pre-production CHV steppings and no benefit on the
production CHV steppings, this patch should not be merged.
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7a69eba..0bfcd83 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4348,7 +4348,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
> I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> I915_WRITE(GEN6_RC_SLEEP, 0);
>
> - I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> + I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
>
> /* allows RC6 residency counter to work */
> I915_WRITE(VLV_COUNTER_CONTROL,
> @@ -4364,7 +4364,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
> /* 3: Enable RC6 */
> if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
> (pcbr >> VLV_PCBR_ADDR_SHIFT))
> - rc6_mode = GEN6_RC_CTL_EI_MODE(1);
> + rc6_mode = GEN7_RC_CTL_TO_MODE;
>
> I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>
> --
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2014-11-04 22:35 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-04 12:51 [PATCH 00/10] drm-intel-collector - update Rodrigo Vivi
2014-11-04 12:51 ` [PATCH 01/10] drm/i915: Check the minimum pitch for the user framebuffer Rodrigo Vivi
2014-11-04 12:51 ` [PATCH 02/10] drm/i915: Make the physical object coherent with GTT Rodrigo Vivi
2014-11-04 12:51 ` [PATCH 03/10] drm/i915/chv: Use timeout mode for RC6 on chv Rodrigo Vivi
2014-11-04 22:36 ` O'Rourke, Tom [this message]
2014-11-04 12:51 ` [PATCH 04/10] drm/i915: Specify bsd rings through exec flag Rodrigo Vivi
2014-11-04 12:51 ` [PATCH 05/10] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam Rodrigo Vivi
2014-11-04 12:51 ` [PATCH 06/10] drm/i915: Enable vblank interrupts for CRC generation Rodrigo Vivi
2014-11-06 8:31 ` Damien Lespiau
2014-11-04 12:51 ` [PATCH 07/10] drm/i915: Move the ban period onto the context Rodrigo Vivi
2014-11-04 12:51 ` [PATCH 08/10] drm/i915: Add ioctl to set per-context parameters Rodrigo Vivi
2014-11-04 12:51 ` [PATCH 09/10] drm/i915: Put logical pipe_control emission into a helper Rodrigo Vivi
2014-11-04 12:51 ` [PATCH 10/10] drm/i915: Add WaCsStallBeforeStateCacheInvalidate:bdw, chv to logical ring Rodrigo Vivi
2014-11-06 0:42 ` [PATCH 00/10] drm-intel-collector - update Rodrigo Vivi
2014-11-06 7:57 ` Ville Syrjälä
2014-11-11 10:20 ` Daniel Vetter
2014-11-11 10:22 ` Chris Wilson
2014-11-11 11:54 ` Daniel Vetter
2014-11-11 11:57 ` Chris Wilson
2014-11-11 14:48 ` Daniel Vetter
2014-11-11 12:16 ` Ville Syrjälä
2014-11-11 12:26 ` Chris Wilson
2014-11-11 12:38 ` Ville Syrjälä
2014-11-11 12:43 ` Chris Wilson
2014-11-11 14:50 ` Daniel Vetter
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