* [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs.
@ 2014-11-08 0:07 Bob Paauwe
2014-11-08 8:55 ` [PATCH] drm/i915: Don't initialize pipe config after shuang.he
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Bob Paauwe @ 2014-11-08 0:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The pipe config needs to be initialized before calling crtc_compute_clock
since this will update the new_config structure DPLL values. Initializing
the new_config structure after calling crtc_compute_clock can result in
incorrect timing values.
This regression was introduced in
commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date: Wed Oct 29 11:32:33 2014 +0200
drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs
and
commit 00d958817dd3daaa452c221387ddaf23d1e4c06f
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date: Wed Oct 29 11:32:36 2014 +0200
drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ff071a7..53f3d3a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10774,7 +10774,11 @@ static int __intel_set_mode(struct drm_crtc *crtc,
}
intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
"[modeset]");
- to_intel_crtc(crtc)->new_config = pipe_config;
+
+ /* mode_set/enable/disable functions rely on a correct pipe
+ * config. */
+ to_intel_crtc(crtc)->config = *pipe_config;
+ to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
}
/*
@@ -10820,10 +10824,6 @@ static int __intel_set_mode(struct drm_crtc *crtc,
*/
if (modeset_pipes) {
crtc->mode = *mode;
- /* mode_set/enable/disable functions rely on a correct pipe
- * config. */
- to_intel_crtc(crtc)->config = *pipe_config;
- to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
/*
* Calculate and store various constants which
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH] drm/i915: Don't initialize pipe config after 2014-11-08 0:07 [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs Bob Paauwe @ 2014-11-08 8:55 ` shuang.he 2014-11-10 10:40 ` [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs Ville Syrjälä 2014-11-10 23:09 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers Bob Paauwe 2 siblings, 0 replies; 11+ messages in thread From: shuang.he @ 2014-11-08 8:55 UTC (permalink / raw) To: shuang.he, intel-gfx, bob.j.paauwe Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate BYT: pass/total=347/348->348/348 PNV: pass/total=326/328->328/328 ILK: pass/total=330/330->317/330 IVB: pass/total=538/546->458/546 SNB: pass/total=549/563->470/563 HSW: pass/total=565/576->483/576 BDW: pass/total=430/435->429/435 -------------------------------------Detailed------------------------------------- test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)... BYT: Intel_gpu_tools, igt_gem_concurrent_blit_prw-bcs-gpu-read-after-write-interruptible, DMESG_WARN(1, M36)PASS(3, M36) -> PASS(4, M36) PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-exclusive-crtc, DMESG_WARN(1, M25)PASS(3, M24) -> DMESG_WARN(3, M24)PASS(1, M24) PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, DMESG_WARN(1, M25)PASS(3, M24) -> DMESG_WARN(3, M24)PASS(1, M24) ILK: Intel_gpu_tools, igt_gem_reset_stats_ban-render, PASS(4, M37M26) -> NO_RESULT(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_3d, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_dpms-off-confusion, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-expired-vblank, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-fences-interruptible, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-interruptible, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-vs-hang, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(2, M26)PASS(2, M26) ILK: Intel_gpu_tools, igt_kms_flip_wf_vblank-interruptible, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(2, M26)PASS(2, M26) ILK: Intel_gpu_tools, igt_kms_flip_wf_vblank-vs-dpms-interruptible, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_wf_vblank-vs-modeset, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_wf_vblank-vs-modeset-interruptible, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_render_gpu-blit, DMESG_WARN(3, M26)PASS(1, M37) -> DMESG_WARN(1, M26)PASS(3, M26) IVB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-early-read, CRASH(1, M4) -> CRASH(3, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-early-read-forked, DMESG_FAIL(1, M4) -> DMESG_FAIL(3, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write, CRASH(1, M4) -> CRASH(3, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-forked, DMESG_FAIL(1, M4) -> DMESG_FAIL(3, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-early-read, CRASH(1, M4) -> CRASH(3, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-early-read-forked, DMESG_FAIL(1, M4) -> DMESG_FAIL(3, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write, CRASH(1, M4) -> CRASH(3, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write-forked, DMESG_FAIL(1, M4) -> DMESG_FAIL(3, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_kms_3d, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-128x128-onscreen, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-128x128-random, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-128x128-sliding, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-offscreen, PASS(1, M4) -> DMESG_WARN(1, M4)TIMEOUT(1, M4)PASS(2, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-onscreen, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-random, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-offscreen, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-onscreen, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-random, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-sliding, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_fence_pin_leak, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_absolute-wf_vblank-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_blocking-absolute-wf_vblank, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_blocking-absolute-wf_vblank-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_bo-too-big-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_busy-flip, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_busy-flip-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_dpms-off-confusion, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_dpms-off-confusion-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_dpms-vs-vblank-race, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_dpms-vs-vblank-race-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_event_leak, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-dpms-off-vs-modeset, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-expired-vblank, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-expired-vblank-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-fences, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-fences-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-vs-hang, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-vs-hang-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-panning, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-vs-hang, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-vs-hang-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_modeset-vs-vblank-race, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_modeset-vs-vblank-race-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_nonexisting-fb, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_nonexisting-fb-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_plain-flip, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_plain-flip-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_tiling_flip-changes-tiling, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_vblank-vs-hang, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_wf_vblank, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_flip_wf_vblank-interruptible, PASS(1, M4) -> DMESG_WARN(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_hang-read-crc-pipe-A, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_hang-read-crc-pipe-B, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_hang-read-crc-pipe-C, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-A, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-A-frame-sequence, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-B, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-B-frame-sequence, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-C, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-C-frame-sequence, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-A-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-A-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-B-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-B-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-C-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-C-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-B-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-B-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-C-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-C-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-A-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-A-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-B-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-B-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-C-plane-1, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-C-plane-2, PASS(1, M4) -> TIMEOUT(1, M4)PASS(3, M4) IVB: Intel_gpu_tools, igt_kms_rotation_crc_primary-rotation, PASS(1, M4) -> TIMEOUT(1, M4)PASS(1, M4) IVB: Intel_gpu_tools, igt_kms_rotation_crc_sprite-rotation, PASS(1, M4) -> TIMEOUT(1, M4) IVB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, PASS(1, M4) -> DMESG_WARN(1, M4) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gpu-bcs-overwrite-source, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-early-read, CRASH(1, M35) -> CRASH(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-early-read-forked, DMESG_FAIL(1, M35) -> DMESG_FAIL(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write, CRASH(1, M35) -> CRASH(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-forked, DMESG_FAIL(1, M35) -> DMESG_FAIL(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-early-read, CRASH(1, M35) -> CRASH(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-early-read-forked, DMESG_FAIL(1, M35) -> DMESG_FAIL(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write, CRASH(1, M35) -> CRASH(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write-forked, DMESG_FAIL(1, M35) -> DMESG_FAIL(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_kms_3d, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-offscreen, DMESG_WARN(1, M35) -> FAIL(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-random, DMESG_WARN(1, M35) -> FAIL(1, M22)DMESG_WARN(2, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, PASS(1, M35) -> FAIL(1, M22)DMESG_WARN(1, M22)PASS(2, M22) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-onscreen, PASS(1, M35) -> FAIL(1, M22)DMESG_WARN(1, M22)PASS(2, M22) SNB: Intel_gpu_tools, igt_kms_fence_pin_leak, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_absolute-wf_vblank, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_absolute-wf_vblank-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_blocking-absolute-wf_vblank, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_blocking-absolute-wf_vblank-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_bo-too-big, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_bo-too-big-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_busy-flip, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_busy-flip-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_dpms-off-confusion, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_dpms-off-confusion-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_dpms-vs-vblank-race, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_dpms-vs-vblank-race-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_event_leak, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-dpms-off-vs-modeset, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-expired-vblank, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-expired-vblank-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-fences, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-fences-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-vs-hang, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-panning, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-vs-hang, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_modeset-vs-vblank-race, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_modeset-vs-vblank-race-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_nonexisting-fb, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_nonexisting-fb-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_plain-flip, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_plain-flip-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_vblank-vs-dpms-rpm, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_vblank-vs-hang, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_vblank-vs-hang-interruptible, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_vblank-vs-modeset-rpm, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_flip_wf_vblank, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_pipe_crc_basic_hang-read-crc-pipe-A, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_pipe_crc_basic_hang-read-crc-pipe-B, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-A, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-A-frame-sequence, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-B-frame-sequence, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-1, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-2, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-1, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-A-plane-1, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-B-plane-1, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-B-plane-2, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-2, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-B-plane-1, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-B-plane-2, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-A-plane-1, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-A-plane-2, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-B-plane-1, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-B-plane-2, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_rotation_crc_primary-rotation, PASS(1, M35) -> FAIL(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_cursor, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_debugfs-forcewake-user, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_debugfs-read, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_dpms-mode-unset-non-lpsp, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_dpms-non-lpsp, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_drm-resources-equal, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_fences, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_fences-dpms, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_gem-execbuf, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_gem-idle, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_gem-mmap-cpu, PASS(1, M35) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_pm_rpm_gem-mmap-gtt, PASS(1, M35) -> DMESG_WARN(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_gem-pread, PASS(1, M35) -> DMESG_WARN(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_i2c, PASS(1, M35) -> DMESG_WARN(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_modeset-non-lpsp, PASS(1, M35) -> DMESG_WARN(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_modeset-non-lpsp-stress-no-wait, PASS(1, M35) -> DMESG_WARN(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_pci-d3-state, PASS(1, M35) -> DMESG_WARN(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_reg-read-ioctl, PASS(1, M35) -> DMESG_WARN(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_rte, PASS(1, M35) -> DMESG_WARN(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_sysfs-read, PASS(1, M35) -> DMESG_WARN(1, M22) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gpu-rcs-early-read-forked, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-early-read, CRASH(1, M40) -> CRASH(3, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-early-read-forked, DMESG_FAIL(1, M40) -> DMESG_FAIL(3, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write, CRASH(1, M40) -> CRASH(3, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-forked, DMESG_FAIL(1, M40) -> DMESG_FAIL(3, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-early-read, CRASH(1, M40) -> CRASH(3, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-early-read-forked, DMESG_FAIL(1, M40) -> DMESG_FAIL(3, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write, CRASH(1, M40) -> CRASH(3, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write-forked, DMESG_FAIL(1, M40) -> DMESG_FAIL(3, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_gem_userptr_blits_coherency-unsync, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-128x128-onscreen, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-128x128-sliding, PASS(1, M40) -> DMESG_WARN(1, M39)TIMEOUT(1, M39)PASS(2, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-offscreen, PASS(1, M40) -> DMESG_WARN(2, M39)TIMEOUT(1, M39)PASS(1, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-onscreen, PASS(1, M40) -> DMESG_WARN(1, M39)TIMEOUT(1, M39)PASS(2, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-random, PASS(1, M40) -> DMESG_WARN(1, M39)TIMEOUT(1, M39)PASS(2, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-offscreen, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-onscreen, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-random, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-sliding, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-size-change, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_fence_pin_leak, PASS(1, M40) -> DMESG_WARN(2, M39)PASS(2, M39) HSW: Intel_gpu_tools, igt_kms_flip_absolute-wf_vblank, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_absolute-wf_vblank-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_blocking-absolute-wf_vblank, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_blocking-absolute-wf_vblank-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_bo-too-big, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_bo-too-big-interruptible, PASS(1, M40) -> DMESG_WARN(2, M39)PASS(2, M39) HSW: Intel_gpu_tools, igt_kms_flip_busy-flip, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_busy-flip-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_dpms-off-confusion, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_dpms-off-confusion-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_dpms-vs-vblank-race, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_dpms-vs-vblank-race-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-dpms-off-vs-modeset, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-expired-vblank, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-expired-vblank-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-fences, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-fences-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-vs-hang, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-vs-hang-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-panning, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-vs-hang, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-vs-hang-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_modeset-vs-vblank-race, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_modeset-vs-vblank-race-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_nonexisting-fb, PASS(1, M40) -> DMESG_WARN(2, M39)PASS(2, M39) HSW: Intel_gpu_tools, igt_kms_flip_nonexisting-fb-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_plain-flip, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_plain-flip-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_tiling_flip-changes-tiling, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_vblank-vs-hang, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_vblank-vs-hang-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_wf_vblank, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_flip_wf_vblank-interruptible, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_bad-nb-words-1, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_hang-read-crc-pipe-A, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_hang-read-crc-pipe-C, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-A, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-A-frame-sequence, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-B, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-B-frame-sequence, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-C, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_pipe_crc_basic_read-crc-pipe-C-frame-sequence, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-1, PASS(1, M40) -> DMESG_WARN(1, M39)TIMEOUT(1, M39)PASS(2, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-A-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-A-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-B-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-B-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-C-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-panning-top-left-pipe-C-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-B-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-B-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-C-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-C-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-A-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-A-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-B-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-B-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-C-plane-1, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_plane_plane-position-hole-pipe-C-plane-2, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_rotation_crc_primary-rotation, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_rotation_crc_sprite-rotation, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39) HSW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, PASS(1, M40) -> DMESG_WARN(1, M39)PASS(3, M39) BDW: Intel_gpu_tools, igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible, PASS(4, M42) -> DMESG_WARN(1, M42)PASS(3, M42) BDW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-early-read, CRASH(1, M42)PASS(3, M42) -> CRASH(3, M42)PASS(1, M42) BDW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write, CRASH(1, M42)PASS(3, M42) -> CRASH(3, M42)PASS(1, M42) BDW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-early-read, CRASH(1, M42)PASS(3, M42) -> CRASH(3, M42)PASS(1, M42) BDW: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write, CRASH(1, M42)DMESG_WARN(1, M42)PASS(2, M42) -> CRASH(3, M42)PASS(1, M42) BDW: Intel_gpu_tools, igt_gem_gtt_hog, DMESG_FAIL(1, M42)PASS(3, M42) -> DMESG_FAIL(3, M42)PASS(1, M42) BDW: Intel_gpu_tools, igt_gem_userptr_blits_forked-sync-interruptible, PASS(4, M42) -> DMESG_WARN(1, M42)PASS(3, M42) BDW: Intel_gpu_tools, igt_gem_userptr_blits_forked-sync-mempressure-interruptible, PASS(4, M42) -> NO_RESULT(1, M42)PASS(3, M42) BDW: Intel_gpu_tools, igt_gem_userptr_blits_forked-sync-multifd-mempressure-normal, PASS(4, M42) -> DMESG_WARN(1, M42)PASS(3, M42) BDW: Intel_gpu_tools, igt_kms_fence_pin_leak, DMESG_WARN(3, M42)PASS(1, M42) -> DMESG_WARN(1, M42)PASS(3, M42) BDW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, DMESG_WARN(3, M42)PASS(1, M42) -> DMESG_WARN(1, M42)PASS(3, M42) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs. 2014-11-08 0:07 [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs Bob Paauwe 2014-11-08 8:55 ` [PATCH] drm/i915: Don't initialize pipe config after shuang.he @ 2014-11-10 10:40 ` Ville Syrjälä 2014-11-10 22:50 ` Bob Paauwe 2014-11-10 23:09 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers Bob Paauwe 2 siblings, 1 reply; 11+ messages in thread From: Ville Syrjälä @ 2014-11-10 10:40 UTC (permalink / raw) To: Bob Paauwe; +Cc: Ander Conselvan de Oliveira, intel-gfx On Fri, Nov 07, 2014 at 04:07:50PM -0800, Bob Paauwe wrote: > The pipe config needs to be initialized before calling crtc_compute_clock > since this will update the new_config structure DPLL values. Initializing > the new_config structure after calling crtc_compute_clock can result in > incorrect timing values. > > This regression was introduced in > > commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > Date: Wed Oct 29 11:32:33 2014 +0200 > > drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs > > and > > commit 00d958817dd3daaa452c221387ddaf23d1e4c06f > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > Date: Wed Oct 29 11:32:36 2014 +0200 > > drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs > > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> > CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index ff071a7..53f3d3a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -10774,7 +10774,11 @@ static int __intel_set_mode(struct drm_crtc *crtc, > } > intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, > "[modeset]"); > - to_intel_crtc(crtc)->new_config = pipe_config; new_config _is_ initialized here. > + > + /* mode_set/enable/disable functions rely on a correct pipe > + * config. */ > + to_intel_crtc(crtc)->config = *pipe_config; > + to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; And this will clobber the old config before we even know if the modeset will succeed. That's not what we want. You didn't really describe the problem you're seeing, so coming up with theories is a bit hard. I guess one problem could be that some piece of code is still looking at crtc->config when it should be looking at crtc->new_config. In any case, I suggest you tell us a bit more before anyone spends too much time guessing. > } > > /* > @@ -10820,10 +10824,6 @@ static int __intel_set_mode(struct drm_crtc *crtc, > */ > if (modeset_pipes) { > crtc->mode = *mode; > - /* mode_set/enable/disable functions rely on a correct pipe > - * config. */ > - to_intel_crtc(crtc)->config = *pipe_config; > - to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; > > /* > * Calculate and store various constants which > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs. 2014-11-10 10:40 ` [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs Ville Syrjälä @ 2014-11-10 22:50 ` Bob Paauwe 0 siblings, 0 replies; 11+ messages in thread From: Bob Paauwe @ 2014-11-10 22:50 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Ander Conselvan de Oliveira, intel-gfx On Mon, 10 Nov 2014 12:40:47 +0200 Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Fri, Nov 07, 2014 at 04:07:50PM -0800, Bob Paauwe wrote: > > The pipe config needs to be initialized before calling crtc_compute_clock > > since this will update the new_config structure DPLL values. Initializing > > the new_config structure after calling crtc_compute_clock can result in > > incorrect timing values. > > > > This regression was introduced in > > > > commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 > > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > > Date: Wed Oct 29 11:32:33 2014 +0200 > > > > drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs > > > > and > > > > commit 00d958817dd3daaa452c221387ddaf23d1e4c06f > > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > > Date: Wed Oct 29 11:32:36 2014 +0200 > > > > drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs > > > > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> > > CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > > --- > > drivers/gpu/drm/i915/intel_display.c | 10 +++++----- > > 1 file changed, 5 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index ff071a7..53f3d3a 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -10774,7 +10774,11 @@ static int __intel_set_mode(struct drm_crtc *crtc, > > } > > intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, > > "[modeset]"); > > - to_intel_crtc(crtc)->new_config = pipe_config; > > new_config _is_ initialized here. > > > + > > + /* mode_set/enable/disable functions rely on a correct pipe > > + * config. */ > > + to_intel_crtc(crtc)->config = *pipe_config; > > + to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; > > And this will clobber the old config before we even know if the modeset > will succeed. That's not what we want. Ahh, I was looking at this wrong before. For some reason I was thinking that when this was done below, it was overwriting something that was set in new_config/pipe_config. > > You didn't really describe the problem you're seeing, so coming up with > theories is a bit hard. I guess one problem could be that some piece of > code is still looking at crtc->config when it should be looking at > crtc->new_config. In any case, I suggest you tell us a bit more before > anyone spends too much time guessing. With the series that changes this to choose DPLLs before disabling CRTCs, my 945 system fails to set the initial mode (no display) and I get this error: Nov 11 03:47:07 localhost kernel: [ 2.086190] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in adjusted_mode.crtc_clock (expected 148500, found 57600) Nov 11 03:47:07 localhost kernel: [ 2.086191] ------------[ cut here ]------------ Nov 11 03:47:07 localhost kernel: [ 2.086238] WARNING: CPU: 1 PID: 56 at /home/bpaauwe/git/otc/drm-intel/drivers/gpu/drm/i915/intel_display.c:10650 check_crtc_state+0x244/0x2ac [i915]() Nov 11 03:47:07 localhost kernel: [ 2.086239] pipe state doesn't match! I bisected it back to the commit referenced above. I had been thinking that something was not getting set property, but your insight that maybe something was using the old values is right. I found where it's doing that. I'll send out a new patch shortly. > > > } > > > > /* > > @@ -10820,10 +10824,6 @@ static int __intel_set_mode(struct drm_crtc *crtc, > > */ > > if (modeset_pipes) { > > crtc->mode = *mode; > > - /* mode_set/enable/disable functions rely on a correct pipe > > - * config. */ > > - to_intel_crtc(crtc)->config = *pipe_config; > > - to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; > > > > /* > > * Calculate and store various constants which > > -- > > 1.8.3.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] drm/i915: Use correct pipe config to update pll dividers. 2014-11-08 0:07 [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs Bob Paauwe 2014-11-08 8:55 ` [PATCH] drm/i915: Don't initialize pipe config after shuang.he 2014-11-10 10:40 ` [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs Ville Syrjälä @ 2014-11-10 23:09 ` Bob Paauwe 2014-11-11 9:16 ` Ander Conselvan de Oliveira 2014-11-11 21:19 ` shuang.he 2 siblings, 2 replies; 11+ messages in thread From: Bob Paauwe @ 2014-11-10 23:09 UTC (permalink / raw) To: intel-gfx; +Cc: Ander Conselvan de Oliveira Use the new pipe config values to calculate the updated pll dividers. This regression was introduced in commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:33 2014 +0200 drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs and commit 00d958817dd3daaa452c221387ddaf23d1e4c06f Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:36 2014 +0200 drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> CC: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ff071a7..601641d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, u32 fp, fp2 = 0; if (IS_PINEVIEW(dev)) { - fp = pnv_dpll_compute_fp(&crtc->config.dpll); + fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); if (reduced_clock) fp2 = pnv_dpll_compute_fp(reduced_clock); } else { - fp = i9xx_dpll_compute_fp(&crtc->config.dpll); + fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); if (reduced_clock) fp2 = i9xx_dpll_compute_fp(reduced_clock); } - crtc->config.dpll_hw_state.fp0 = fp; + crtc->new_config->dpll_hw_state.fp0 = fp; crtc->lowfreq_avail = false; if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && reduced_clock && i915.powersave) { - crtc->config.dpll_hw_state.fp1 = fp2; + crtc->new_config->dpll_hw_state.fp1 = fp2; crtc->lowfreq_avail = true; } else { - crtc->config.dpll_hw_state.fp1 = fp; + crtc->new_config->dpll_hw_state.fp1 = fp; } } -- 1.8.3.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Use correct pipe config to update pll dividers. 2014-11-10 23:09 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers Bob Paauwe @ 2014-11-11 9:16 ` Ander Conselvan de Oliveira 2014-11-11 17:29 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers. V2 Bob Paauwe 2014-11-11 21:19 ` shuang.he 1 sibling, 1 reply; 11+ messages in thread From: Ander Conselvan de Oliveira @ 2014-11-11 9:16 UTC (permalink / raw) To: Bob Paauwe, intel-gfx Hi Bob, Thanks for the patch. Just a small comment below. On 11/11/2014 01:09 AM, Bob Paauwe wrote: > Use the new pipe config values to calculate the updated pll dividers. > > This regression was introduced in > > commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > Date: Wed Oct 29 11:32:33 2014 +0200 > > drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs > > and > > commit 00d958817dd3daaa452c221387ddaf23d1e4c06f > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > Date: Wed Oct 29 11:32:36 2014 +0200 > > drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs > > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> > CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > CC: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index ff071a7..601641d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, > u32 fp, fp2 = 0; > > if (IS_PINEVIEW(dev)) { > - fp = pnv_dpll_compute_fp(&crtc->config.dpll); > + fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); > if (reduced_clock) > fp2 = pnv_dpll_compute_fp(reduced_clock); > } else { > - fp = i9xx_dpll_compute_fp(&crtc->config.dpll); > + fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); > if (reduced_clock) > fp2 = i9xx_dpll_compute_fp(reduced_clock); > } > > - crtc->config.dpll_hw_state.fp0 = fp; > + crtc->new_config->dpll_hw_state.fp0 = fp; > > crtc->lowfreq_avail = false; > if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && This needs to be changed to intel_pipe_will_have_type(), so that it looks at the new configuration instead of the current one. With that fixed, Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > reduced_clock && i915.powersave) { > - crtc->config.dpll_hw_state.fp1 = fp2; > + crtc->new_config->dpll_hw_state.fp1 = fp2; > crtc->lowfreq_avail = true; > } else { > - crtc->config.dpll_hw_state.fp1 = fp; > + crtc->new_config->dpll_hw_state.fp1 = fp; > } > } > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] drm/i915: Use correct pipe config to update pll dividers. V2 2014-11-11 9:16 ` Ander Conselvan de Oliveira @ 2014-11-11 17:29 ` Bob Paauwe 2014-11-11 18:34 ` Jesse Barnes 2014-11-12 14:08 ` [PATCH] drm/i915: Use correct pipe config to update pll shuang.he 0 siblings, 2 replies; 11+ messages in thread From: Bob Paauwe @ 2014-11-11 17:29 UTC (permalink / raw) To: intel-gfx; +Cc: Ander Conselvan de Oliveira Use the new pipe config values to calculate the updated pll dividers. This regression was introduced in commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:33 2014 +0200 drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs and commit 00d958817dd3daaa452c221387ddaf23d1e4c06f Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:36 2014 +0200 drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs v2: Use intel_pipe_will_have_type() to look at new configuration - Ander Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ff071a7..667d72a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, u32 fp, fp2 = 0; if (IS_PINEVIEW(dev)) { - fp = pnv_dpll_compute_fp(&crtc->config.dpll); + fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); if (reduced_clock) fp2 = pnv_dpll_compute_fp(reduced_clock); } else { - fp = i9xx_dpll_compute_fp(&crtc->config.dpll); + fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); if (reduced_clock) fp2 = i9xx_dpll_compute_fp(reduced_clock); } - crtc->config.dpll_hw_state.fp0 = fp; + crtc->new_config->dpll_hw_state.fp0 = fp; crtc->lowfreq_avail = false; - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && + if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && reduced_clock && i915.powersave) { - crtc->config.dpll_hw_state.fp1 = fp2; + crtc->new_config->dpll_hw_state.fp1 = fp2; crtc->lowfreq_avail = true; } else { - crtc->config.dpll_hw_state.fp1 = fp; + crtc->new_config->dpll_hw_state.fp1 = fp; } } -- 1.8.3.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Use correct pipe config to update pll dividers. V2 2014-11-11 17:29 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers. V2 Bob Paauwe @ 2014-11-11 18:34 ` Jesse Barnes 2014-11-12 9:23 ` Daniel Vetter 2014-11-12 14:08 ` [PATCH] drm/i915: Use correct pipe config to update pll shuang.he 1 sibling, 1 reply; 11+ messages in thread From: Jesse Barnes @ 2014-11-11 18:34 UTC (permalink / raw) To: Bob Paauwe; +Cc: Ander Conselvan de Oliveira, intel-gfx On Tue, 11 Nov 2014 09:29:18 -0800 Bob Paauwe <bob.j.paauwe@intel.com> wrote: > Use the new pipe config values to calculate the updated pll dividers. > > This regression was introduced in > > commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 > Author: Ander Conselvan de Oliveira > <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:33 > 2014 +0200 > > drm/i915: Add infrastructure for choosing DPLLs before disabling > crtcs > > and > > commit 00d958817dd3daaa452c221387ddaf23d1e4c06f > Author: Ander Conselvan de Oliveira > <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:36 > 2014 +0200 > > drm/i915: Covert remaining platforms to choose DPLLS > before disabling CRTCs > > v2: Use intel_pipe_will_have_type() to look at new configuration - > Ander > > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> > CC: Ander Conselvan de Oliveira > <ander.conselvan.de.oliveira@intel.com> --- > drivers/gpu/drm/i915/intel_display.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c index ff071a7..667d72a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct > intel_crtc *crtc, u32 fp, fp2 = 0; > > if (IS_PINEVIEW(dev)) { > - fp = pnv_dpll_compute_fp(&crtc->config.dpll); > + fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); > if (reduced_clock) > fp2 = pnv_dpll_compute_fp(reduced_clock); > } else { > - fp = i9xx_dpll_compute_fp(&crtc->config.dpll); > + fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); > if (reduced_clock) > fp2 = i9xx_dpll_compute_fp(reduced_clock); > } > > - crtc->config.dpll_hw_state.fp0 = fp; > + crtc->new_config->dpll_hw_state.fp0 = fp; > > crtc->lowfreq_avail = false; > - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && > + if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && > reduced_clock && i915.powersave) { > - crtc->config.dpll_hw_state.fp1 = fp2; > + crtc->new_config->dpll_hw_state.fp1 = fp2; > crtc->lowfreq_avail = true; > } else { > - crtc->config.dpll_hw_state.fp1 = fp; > + crtc->new_config->dpll_hw_state.fp1 = fp; > } > } > Fixes things on my 945 here. Thanks. Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Use correct pipe config to update pll dividers. V2 2014-11-11 18:34 ` Jesse Barnes @ 2014-11-12 9:23 ` Daniel Vetter 0 siblings, 0 replies; 11+ messages in thread From: Daniel Vetter @ 2014-11-12 9:23 UTC (permalink / raw) To: Jesse Barnes; +Cc: Ander Conselvan de Oliveira, intel-gfx On Tue, Nov 11, 2014 at 10:34:15AM -0800, Jesse Barnes wrote: > On Tue, 11 Nov 2014 09:29:18 -0800 > Bob Paauwe <bob.j.paauwe@intel.com> wrote: > > > Use the new pipe config values to calculate the updated pll dividers. > > > > This regression was introduced in > > > > commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 > > Author: Ander Conselvan de Oliveira > > <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:33 > > 2014 +0200 > > > > drm/i915: Add infrastructure for choosing DPLLs before disabling > > crtcs > > > > and > > > > commit 00d958817dd3daaa452c221387ddaf23d1e4c06f > > Author: Ander Conselvan de Oliveira > > <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:36 > > 2014 +0200 > > > > drm/i915: Covert remaining platforms to choose DPLLS > > before disabling CRTCs > > > > v2: Use intel_pipe_will_have_type() to look at new configuration - > > Ander > > > > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> > > CC: Ander Conselvan de Oliveira > > <ander.conselvan.de.oliveira@intel.com> --- Queued for -next, thanks for the patch. -Daniel > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c index ff071a7..667d72a 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct > > intel_crtc *crtc, u32 fp, fp2 = 0; > > > > if (IS_PINEVIEW(dev)) { > > - fp = pnv_dpll_compute_fp(&crtc->config.dpll); > > + fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); > > if (reduced_clock) > > fp2 = pnv_dpll_compute_fp(reduced_clock); > > } else { > > - fp = i9xx_dpll_compute_fp(&crtc->config.dpll); > > + fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); > > if (reduced_clock) > > fp2 = i9xx_dpll_compute_fp(reduced_clock); > > } > > > > - crtc->config.dpll_hw_state.fp0 = fp; > > + crtc->new_config->dpll_hw_state.fp0 = fp; > > > > crtc->lowfreq_avail = false; > > - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && > > + if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && > > reduced_clock && i915.powersave) { > > - crtc->config.dpll_hw_state.fp1 = fp2; > > + crtc->new_config->dpll_hw_state.fp1 = fp2; > > crtc->lowfreq_avail = true; > > } else { > > - crtc->config.dpll_hw_state.fp1 = fp; > > + crtc->new_config->dpll_hw_state.fp1 = fp; > > } > > } > > > > Fixes things on my 945 here. Thanks. > > Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org> > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Use correct pipe config to update pll 2014-11-11 17:29 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers. V2 Bob Paauwe 2014-11-11 18:34 ` Jesse Barnes @ 2014-11-12 14:08 ` shuang.he 1 sibling, 0 replies; 11+ messages in thread From: shuang.he @ 2014-11-12 14:08 UTC (permalink / raw) To: shuang.he, intel-gfx, bob.j.paauwe Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate BYT: pass/total=247/348->276/348 PNV: pass/total=326/328->327/328 ILK: pass/total=329/330->330/330 IVB: pass/total=544/546->544/546 SNB: pass/total=384/384->383/384 HSW: pass/total=583/588->586/588 BDW: pass/total=435/435->433/435 -------------------------------------Detailed------------------------------------- test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)... BYT: Intel_gpu_tools, igt_drv_hangman_error-state-basic, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-blt, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-bsd, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-debugfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-sysfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc-lut, NSPT(1, M38)PASS(15, M31M29M38) -> NSPT(1, M29)PASS(3, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-blt, BLACKLIST(1, M31)DMESG_WARN(11, M31M36M29)PASS(13, M31M36M38) -> DMESG_WARN(2, M29)PASS(2, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-bsd, BLACKLIST(1, M31)DMESG_WARN(9, M36M29M31)PASS(15, M31M29M38M36) -> DMESG_WARN(1, M29)PASS(3, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-blt, BLACKLIST(1, M31)DMESG_WARN(11, M31M36M29)PASS(13, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-bsd, BLACKLIST(1, M31)DMESG_WARN(12, M31M36M29)PASS(12, M31M36M29M38) -> DMESG_WARN(2, M29)PASS(2, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-blt, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-bsd, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_params, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_params-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-blt, BLACKLIST(1, M31)DMESG_WARN(16, M31M36M29)PASS(8, M29M38M36) -> DMESG_WARN(3, M29)PASS(1, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-bsd, BLACKLIST(1, M31)DMESG_WARN(14, M31M36M29)PASS(10, M36M38M29) -> DMESG_WARN(2, M29)PASS(2, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-blt, BLACKLIST(1, M31)DMESG_WARN(8, M36M29M31)PASS(16, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-bsd, BLACKLIST(1, M31)DMESG_WARN(9, M36M29M31)PASS(15, M31M36M29M38) -> DMESG_WARN(1, M29)PASS(3, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_gem_reset_stats_unrelated-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) BYT: Intel_gpu_tools, igt_drv_hangman_ring-stop-sysfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29) PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-exclusive-crtc, DMESG_WARN(1, M25)PASS(6, M24) -> DMESG_WARN(3, M24)PASS(1, M24) PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, DMESG_WARN(1, M25)TIMEOUT(15, M7M25M24M23)PASS(3, M24) -> DMESG_WARN(3, M24)TIMEOUT(1, M24) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-interruptible, DMESG_WARN(2, M26)PASS(26, M37M26M6) -> PASS(4, M37) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(27, M21M4M34) -> PASS(4, M4) IVB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(15, M34M21M4)PASS(1, M34) -> TIMEOUT(1, M4)PASS(3, M4) SNB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(3, M35)PASS(1, M35) -> TIMEOUT(1, M35)PASS(3, M35) HSW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, PASS(1, M40) -> TIMEOUT(1, M20)PASS(3, M20) HSW: Intel_gpu_tools, igt_pm_rpm_legacy-planes, TIMEOUT(1, M40) -> TIMEOUT(3, M20)PASS(1, M20) HSW: Intel_gpu_tools, igt_pm_rpm_legacy-planes-dpms, TIMEOUT(1, M40) -> TIMEOUT(3, M20)PASS(1, M20) HSW: Intel_gpu_tools, igt_pm_rpm_universal-planes, TIMEOUT(1, M40) -> TIMEOUT(1, M20)PASS(1, M20) HSW: Intel_gpu_tools, igt_pm_rpm_universal-planes-dpms, TIMEOUT(1, M40) -> PASS(1, M20) BDW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(15, M28M42M30)PASS(1, M42) -> TIMEOUT(1, M30)PASS(3, M30) BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(31, M42M30M28) -> DMESG_WARN(1, M30)PASS(3, M30) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Use correct pipe config to update pll 2014-11-10 23:09 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers Bob Paauwe 2014-11-11 9:16 ` Ander Conselvan de Oliveira @ 2014-11-11 21:19 ` shuang.he 1 sibling, 0 replies; 11+ messages in thread From: shuang.he @ 2014-11-11 21:19 UTC (permalink / raw) To: shuang.he, intel-gfx, bob.j.paauwe Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate BYT: pass/total=247/348->277/348 PNV: pass/total=326/328->328/328 ILK: pass/total=329/330->326/330 IVB: pass/total=544/546->545/546 SNB: pass/total=558/563->559/563 HSW: pass/total=572/577->572/577 BDW: pass/total=435/435->434/435 -------------------------------------Detailed------------------------------------- test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)... BYT: Intel_gpu_tools, igt_drv_hangman_error-state-basic, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-blt, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-bsd, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-debugfs-entry, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-sysfs-entry, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-blt, BLACKLIST(1, M31)DMESG_WARN(7, M31M36M29)PASS(8, M31M36M38) -> DMESG_WARN(2, M36)PASS(2, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-bsd, BLACKLIST(1, M31)DMESG_WARN(6, M36M29)PASS(9, M31M29M38M36) -> DMESG_WARN(2, M36)PASS(2, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-blt, BLACKLIST(1, M31)DMESG_WARN(7, M31M36M29)PASS(8, M31M36M29M38) -> DMESG_WARN(2, M36)PASS(2, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-bsd, BLACKLIST(1, M31)DMESG_WARN(7, M31M36M29)PASS(8, M31M36M29M38) -> DMESG_WARN(3, M36)PASS(1, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-blt, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-bsd, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_params, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_params-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-blt, BLACKLIST(1, M31)DMESG_WARN(10, M31M36M29)PASS(5, M29M38M36) -> DMESG_WARN(3, M36)PASS(1, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-bsd, BLACKLIST(1, M31)DMESG_WARN(10, M31M36M29)PASS(5, M36M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-blt, BLACKLIST(1, M31)DMESG_WARN(6, M36M29)PASS(9, M31M36M29M38) -> DMESG_WARN(2, M36)PASS(2, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-bsd, BLACKLIST(1, M31)DMESG_WARN(7, M36M29)PASS(8, M31M36M29M38) -> DMESG_WARN(1, M36)PASS(3, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-ctx-render, BLACKLIST(1, M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-render, BLACKLIST(1, M31)PASS(14, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_unrelated-ctx-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_ring-stop-sysfs-entry, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M36) PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-exclusive-crtc, DMESG_WARN(1, M25)PASS(6, M24) -> DMESG_WARN(3, M24)PASS(1, M24) PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, DMESG_WARN(1, M25)TIMEOUT(7, M7M25M24)PASS(3, M24) -> DMESG_WARN(3, M24)PASS(1, M24) ILK: Intel_gpu_tools, igt_kms_pipe_crc_basic_bad-nb-words-1, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-fences-interruptible, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(9, M21M4) -> PASS(4, M4) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, DMESG_WARN(1, M35)PASS(9, M35M22) -> PASS(4, M35) BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(16, M42M30M28) -> DMESG_WARN(1, M28)PASS(3, M28) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2014-11-12 14:10 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-11-08 0:07 [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs Bob Paauwe 2014-11-08 8:55 ` [PATCH] drm/i915: Don't initialize pipe config after shuang.he 2014-11-10 10:40 ` [PATCH] drm/i915: Don't initialize pipe config after choosing DPLLs Ville Syrjälä 2014-11-10 22:50 ` Bob Paauwe 2014-11-10 23:09 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers Bob Paauwe 2014-11-11 9:16 ` Ander Conselvan de Oliveira 2014-11-11 17:29 ` [PATCH] drm/i915: Use correct pipe config to update pll dividers. V2 Bob Paauwe 2014-11-11 18:34 ` Jesse Barnes 2014-11-12 9:23 ` Daniel Vetter 2014-11-12 14:08 ` [PATCH] drm/i915: Use correct pipe config to update pll shuang.he 2014-11-11 21:19 ` shuang.he
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