* [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend @ 2014-11-11 14:48 Jani Nikula 2014-11-11 14:48 ` [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS paths Jani Nikula 2014-11-11 15:09 ` [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend Ville Syrjälä 0 siblings, 2 replies; 7+ messages in thread From: Jani Nikula @ 2014-11-11 14:48 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, shuang.he Don't save the panel power sequencer register on vlv/chv for two simple reasons. First, these are the wrong registers to save to begin with. Second, they are not restored anyway. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_suspend.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 043123c77a1f..bd8adf2ca7d8 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -208,7 +208,6 @@ static void i915_save_display(struct drm_device *dev) if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); } else if (IS_VALLEYVIEW(dev)) { - dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); dev_priv->regfile.saveBLC_HIST_CTL = @@ -230,7 +229,7 @@ static void i915_save_display(struct drm_device *dev) dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); - } else { + } else if (!IS_VALLEYVIEW(dev)) { dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR); -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS paths 2014-11-11 14:48 [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend Jani Nikula @ 2014-11-11 14:48 ` Jani Nikula 2014-11-11 15:06 ` Ville Syrjälä 2014-11-12 5:28 ` [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS shuang.he 2014-11-11 15:09 ` [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend Ville Syrjälä 1 sibling, 2 replies; 7+ messages in thread From: Jani Nikula @ 2014-11-11 14:48 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, shuang.he Since RSTDBYCTL is only saved on non-KMS path in within i915_save_state, move the restore in i915_restore_state for symmetry. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- UNTESTED!!! --- drivers/gpu/drm/i915/i915_suspend.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index bd8adf2ca7d8..26b6bf9261ca 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -271,8 +271,6 @@ static void i915_restore_display(struct drm_device *dev) I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); - I915_WRITE(RSTDBYCTL, - dev_priv->regfile.saveMCHBAR_RENDER_STANDBY); } else if (IS_VALLEYVIEW(dev)) { I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A), dev_priv->regfile.saveBLC_HIST_CTL); @@ -367,6 +365,8 @@ int i915_restore_state(struct drm_device *dev) I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR); I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR); I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG); + I915_WRITE(RSTDBYCTL, + dev_priv->regfile.saveMCHBAR_RENDER_STANDBY); } else { I915_WRITE(IER, dev_priv->regfile.saveIER); I915_WRITE(IMR, dev_priv->regfile.saveIMR); -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS paths 2014-11-11 14:48 ` [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS paths Jani Nikula @ 2014-11-11 15:06 ` Ville Syrjälä 2014-11-12 5:28 ` [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS shuang.he 1 sibling, 0 replies; 7+ messages in thread From: Ville Syrjälä @ 2014-11-11 15:06 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, shuang.he On Tue, Nov 11, 2014 at 04:48:04PM +0200, Jani Nikula wrote: > Since RSTDBYCTL is only saved on non-KMS path in within i915_save_state, > move the restore in i915_restore_state for symmetry. Makes sense. And IIRC this is an ilk-only register anyway, so frobbing it on snb+ is dubious at best. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > --- > > UNTESTED!!! > --- > drivers/gpu/drm/i915/i915_suspend.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c > index bd8adf2ca7d8..26b6bf9261ca 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -271,8 +271,6 @@ static void i915_restore_display(struct drm_device *dev) > I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); > I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); > I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); > - I915_WRITE(RSTDBYCTL, > - dev_priv->regfile.saveMCHBAR_RENDER_STANDBY); > } else if (IS_VALLEYVIEW(dev)) { > I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A), > dev_priv->regfile.saveBLC_HIST_CTL); > @@ -367,6 +365,8 @@ int i915_restore_state(struct drm_device *dev) > I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR); > I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR); > I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG); > + I915_WRITE(RSTDBYCTL, > + dev_priv->regfile.saveMCHBAR_RENDER_STANDBY); > } else { > I915_WRITE(IER, dev_priv->regfile.saveIER); > I915_WRITE(IMR, dev_priv->regfile.saveIMR); > -- > 2.1.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS 2014-11-11 14:48 ` [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS paths Jani Nikula 2014-11-11 15:06 ` Ville Syrjälä @ 2014-11-12 5:28 ` shuang.he 1 sibling, 0 replies; 7+ messages in thread From: shuang.he @ 2014-11-12 5:28 UTC (permalink / raw) To: shuang.he, intel-gfx, jani.nikula Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate BYT: pass/total=247/348->277/348 PNV: pass/total=326/328->324/328 ILK: pass/total=329/330->330/330 IVB: pass/total=544/546->545/546 SNB: pass/total=558/563->562/563 HSW: pass/total=586/591->590/591 BDW: pass/total=435/435->434/435 -------------------------------------Detailed------------------------------------- test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)... BYT: Intel_gpu_tools, igt_drv_hangman_error-state-basic, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-blt, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-bsd, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-debugfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-sysfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-blt, BLACKLIST(1, M31)DMESG_WARN(11, M31M36M29)PASS(13, M31M36M38) -> DMESG_WARN(2, M36)PASS(2, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-bsd, BLACKLIST(1, M31)DMESG_WARN(9, M36M29M31)PASS(15, M31M29M38M36) -> DMESG_WARN(3, M36)PASS(1, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-blt, BLACKLIST(1, M31)DMESG_WARN(11, M31M36M29)PASS(13, M31M36M29M38) -> DMESG_WARN(2, M36)PASS(2, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-bsd, BLACKLIST(1, M31)DMESG_WARN(12, M31M36M29)PASS(12, M31M36M29M38) -> DMESG_WARN(3, M36)PASS(1, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-blt, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-bsd, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_params, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_params-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-blt, BLACKLIST(1, M31)DMESG_WARN(16, M31M36M29)PASS(8, M29M38M36) -> DMESG_WARN(3, M36)PASS(1, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-bsd, BLACKLIST(1, M31)DMESG_WARN(14, M31M36M29)PASS(10, M36M38M29) -> DMESG_WARN(1, M36)PASS(3, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-blt, BLACKLIST(1, M31)DMESG_WARN(8, M36M29M31)PASS(16, M31M36M29M38) -> DMESG_WARN(2, M36)PASS(2, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-bsd, BLACKLIST(1, M31)DMESG_WARN(9, M36M29M31)PASS(15, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_gem_reset_stats_unrelated-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) BYT: Intel_gpu_tools, igt_drv_hangman_ring-stop-sysfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M36) PNV: Intel_gpu_tools, igt_drv_hangman_error-state-basic, PASS(10, M25M23) -> DMESG_WARN(1, M23)PASS(3, M23) PNV: Intel_gpu_tools, igt_gem_linear_blits_normal, NSPT(15, M23M7)PASS(1, M25) -> NSPT(4, M23) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-interruptible, DMESG_WARN(2, M26)PASS(26, M37M26M6) -> PASS(4, M37) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(18, M21M4M34) -> PASS(4, M4) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-random, PASS(4, M35M22) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, DMESG_WARN(1, M35)PASS(12, M35M22) -> PASS(4, M22) SNB: Intel_gpu_tools, igt_pm_rpm_legacy-planes, TIMEOUT(1, M35) -> TIMEOUT(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_legacy-planes-dpms, TIMEOUT(1, M35) -> TIMEOUT(3, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_universal-planes, TIMEOUT(1, M35) -> TIMEOUT(2, M22)PASS(1, M22) SNB: Intel_gpu_tools, igt_pm_rpm_universal-planes-dpms, TIMEOUT(1, M35) -> PASS(1, M22) HSW: Intel_gpu_tools, igt_pm_rpm_legacy-planes, TIMEOUT(1, M40) -> TIMEOUT(3, M19)PASS(1, M19) HSW: Intel_gpu_tools, igt_pm_rpm_legacy-planes-dpms, TIMEOUT(1, M40) -> TIMEOUT(3, M19)PASS(1, M19) HSW: Intel_gpu_tools, igt_pm_rpm_universal-planes, TIMEOUT(1, M40) -> TIMEOUT(2, M19)PASS(1, M19) HSW: Intel_gpu_tools, igt_pm_rpm_universal-planes-dpms, TIMEOUT(1, M40) -> PASS(1, M19) BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(28, M42M30M28) -> DMESG_WARN(1, M30)PASS(3, M30) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend 2014-11-11 14:48 [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend Jani Nikula 2014-11-11 14:48 ` [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS paths Jani Nikula @ 2014-11-11 15:09 ` Ville Syrjälä 2014-11-12 7:52 ` Jani Nikula 1 sibling, 1 reply; 7+ messages in thread From: Ville Syrjälä @ 2014-11-11 15:09 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, shuang.he On Tue, Nov 11, 2014 at 04:48:03PM +0200, Jani Nikula wrote: > Don't save the panel power sequencer register on vlv/chv for two simple > reasons. First, these are the wrong registers to save to begin > with. Second, they are not restored anyway. Indeed. I also like how the display save/restore functions look nothing alike. Scary piece of code this, hopefully someone will kill it all at some point... But anyways, patch is good, so: Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_suspend.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c > index 043123c77a1f..bd8adf2ca7d8 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -208,7 +208,6 @@ static void i915_save_display(struct drm_device *dev) > if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) > dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); > } else if (IS_VALLEYVIEW(dev)) { > - dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); > dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); > > dev_priv->regfile.saveBLC_HIST_CTL = > @@ -230,7 +229,7 @@ static void i915_save_display(struct drm_device *dev) > dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); > dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); > dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); > - } else { > + } else if (!IS_VALLEYVIEW(dev)) { > dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); > dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); > dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR); > -- > 2.1.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend 2014-11-11 15:09 ` [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend Ville Syrjälä @ 2014-11-12 7:52 ` Jani Nikula 2014-11-12 9:40 ` Daniel Vetter 0 siblings, 1 reply; 7+ messages in thread From: Jani Nikula @ 2014-11-12 7:52 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, shuang.he On Tue, 11 Nov 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Tue, Nov 11, 2014 at 04:48:03PM +0200, Jani Nikula wrote: >> Don't save the panel power sequencer register on vlv/chv for two simple >> reasons. First, these are the wrong registers to save to begin >> with. Second, they are not restored anyway. > > Indeed. I also like how the display save/restore functions look nothing > alike. Scary piece of code this, hopefully someone will kill it all at > some point... Yup, one patch at a time! Jani. > > But anyways, patch is good, so: > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/i915_suspend.c | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c >> index 043123c77a1f..bd8adf2ca7d8 100644 >> --- a/drivers/gpu/drm/i915/i915_suspend.c >> +++ b/drivers/gpu/drm/i915/i915_suspend.c >> @@ -208,7 +208,6 @@ static void i915_save_display(struct drm_device *dev) >> if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) >> dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); >> } else if (IS_VALLEYVIEW(dev)) { >> - dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); >> dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); >> >> dev_priv->regfile.saveBLC_HIST_CTL = >> @@ -230,7 +229,7 @@ static void i915_save_display(struct drm_device *dev) >> dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); >> dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); >> dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); >> - } else { >> + } else if (!IS_VALLEYVIEW(dev)) { >> dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); >> dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); >> dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR); >> -- >> 2.1.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend 2014-11-12 7:52 ` Jani Nikula @ 2014-11-12 9:40 ` Daniel Vetter 0 siblings, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2014-11-12 9:40 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, shuang.he On Wed, Nov 12, 2014 at 09:52:20AM +0200, Jani Nikula wrote: > On Tue, 11 Nov 2014, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > > On Tue, Nov 11, 2014 at 04:48:03PM +0200, Jani Nikula wrote: > >> Don't save the panel power sequencer register on vlv/chv for two simple > >> reasons. First, these are the wrong registers to save to begin > >> with. Second, they are not restored anyway. > > > > Indeed. I also like how the display save/restore functions look nothing > > alike. Scary piece of code this, hopefully someone will kill it all at > > some point... > > Yup, one patch at a time! Yeah that effort stalled a bit unfortunately, thanks for picking it up. Hopefully we can clear out the remaining gunk when we remove the UMS code. At least we should see a lot clearer what's still left. > > But anyways, patch is good, so: > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Both patches merged, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2014-11-12 9:40 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-11-11 14:48 [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend Jani Nikula 2014-11-11 14:48 ` [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS paths Jani Nikula 2014-11-11 15:06 ` Ville Syrjälä 2014-11-12 5:28 ` [PATCH 2/2] drm/i915: restore RSTDBYCTL only on non-KMS shuang.he 2014-11-11 15:09 ` [PATCH 1/2] drm/i915/vlv: don't save panel power sequencer registers on suspend Ville Syrjälä 2014-11-12 7:52 ` Jani Nikula 2014-11-12 9:40 ` Daniel Vetter
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