Re: [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > 
> > As per latest pm guide, we need to do this also on
> > past hsw.
> 
> Yep, matches the doc.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
> see such a thing documented in the HSW PM guide I have here. Maybe we can
> just drop the HSW special case?
> 
> Also I wonder if we want this on CHV too. I should probably know, but I
> dont't. I'll go bash some registers and see what they say...

So the register doesn't seem to exist on CHV. All I get is 0x0, no
matter if the GT is idle or busy. rc6 residency keeps ticking along
at a constant rate so it seems to be in rc6 when I tried this.

# ./intel_reg_read 0x13805c
0x13805C : 0x0
# IGT_NO_FORCEWAKE=1 ./intel_reg_read 0x13805c
0x13805C : 0x0

On IVB it clearly works:
# ./intel_reg_read 0x13805c
0x13805C : 0x40000000
# IGT_NO_FORCEWAKE=1 ./intel_reg_read 0x13805c
0x13805C : 0x30303

I think someone needs to try this on VLV too...

> 
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 6a0c3fb..86a755a 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -120,8 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
> >  		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
> >  
> >  	/* WaRsForcewakeWaitTC0:ivb,hsw */
> > -	if (INTEL_INFO(dev_priv->dev)->gen < 8)
> > -		__gen6_gt_wait_for_thread_c0(dev_priv);
> > +	__gen6_gt_wait_for_thread_c0(dev_priv);
> >  }
> >  
> >  static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> > -- 
> > 1.9.3
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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