From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 6/6] x86: Use clwb in drm_clflush_virt_range Date: Thu, 13 Nov 2014 19:33:54 +0200 Message-ID: <20141113173354.GT10649@intel.com> References: <1415731396-19364-1-git-send-email-ross.zwisler@linux.intel.com> <1415731396-19364-7-git-send-email-ross.zwisler@linux.intel.com> <5464220D.6090204@amacapital.net> <20141113112017.GA14416@pd.tnic> <20141113171133.GD14070@pd.tnic> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <20141113171133.GD14070@pd.tnic> Sender: linux-kernel-owner@vger.kernel.org To: Borislav Petkov Cc: Andy Lutomirski , intel-gfx@lists.freedesktop.org, X86 ML , "linux-kernel@vger.kernel.org" , DRI , Ingo Molnar , Ross Zwisler , H Peter Anvin , Thomas Gleixner List-Id: intel-gfx@lists.freedesktop.org On Thu, Nov 13, 2014 at 06:11:33PM +0100, Borislav Petkov wrote: > On Thu, Nov 13, 2014 at 08:38:23AM -0800, Andy Lutomirski wrote: > > On Nov 13, 2014 3:20 AM, "Borislav Petkov" wrote: > > > > > > On Wed, Nov 12, 2014 at 07:14:21PM -0800, Andy Lutomirski wrote: > > > > On 11/11/2014 10:43 AM, Ross Zwisler wrote: > > > > > If clwb is available on the system, use it in drm_clflush_vir= t_range. > > > > > If clwb is not available, fall back to clflushopt if you can. > > > > > If clflushopt is not supported, fall all the way back to clfl= ush. > > > > > > > > I don't know exactly what drm_clflush_virt_range (and the other > > > > functions you're modifying similarly) are for, but it seems pla= usible to > > > > me that they're used before reads to make sure that non-coheren= t memory > > > > sees updated data. If that's true, then this will break it. > > > > > > Why would it break it? The updated cachelines will be in memory a= nd > > > subsequent reads will be serviced from the cache instead from goi= ng to > > > memory as it is not invalidated as it would be by CLFLUSH. > > > > > > /me is puzzled. > >=20 > > Suppose you map some device memory WB, and then the device > > non-coherently updates. If you want the CPU to see it, you need > > clflush or clflushopt. Some architectures might do this for > > dma_sync_single_for_cpu with DMA_FROM_DEVICE. >=20 > Ah, you're talking about the other way around - the device does the > writes. Well, the usage sites are all in i915*, maybe we should ask > them - it looks to me like this is only the CPU making stuff visible = in > the shared buffer but I don't know that code... intel-gfx CCed althou= gh > dri-devel is already on CC. We use it both ways in i915. So please don't break it. --=20 Ville Syrj=E4l=E4 Intel OTC