From: Daniel Vetter <daniel@ffwll.ch>
To: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Vivi, Rodrigo" <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 04/10] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions
Date: Fri, 14 Nov 2014 11:02:14 +0100 [thread overview]
Message-ID: <20141114100214.GF25711@phenom.ffwll.local> (raw)
In-Reply-To: <CABVU7+uoC42Y0pTEUTso7khj7VobxSokcMK7-m5tOyw4KpzWjA@mail.gmail.com>
On Thu, Nov 13, 2014 at 07:33:21PM -0500, Rodrigo Vivi wrote:
> On Thu, Nov 6, 2014 at 1:32 PM, R, Durgadoss <durgadoss.r@intel.com> wrote:
> > I see we are keeping the source active during PSR.
> > Making this '0' may provide better power savings,
> > but we need to manage a lot of hassle during PSR exit..
> > (like Link training, DPIO/PLL bring up etc..)
>
> Also I think this blocked sink crc to work. So we wouldn't be able to
> validate it.
> Although there are other things blocking that tests :(
> But I can double check that anyway.
Well we only need to wake up dp aux to get the sink crc, which should just
be the power well. There shouldn't be any need to wake up the source port
at all. So I don't expect big issues here if we do this. Yeah, I'm an
optimist as ever ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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next prev parent reply other threads:[~2014-11-14 10:01 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-28 18:45 [PATCH 00/10] PSR VLV-Braytrail and CHV-Braswell Rodrigo Vivi
2014-10-28 18:45 ` [PATCH 01/10] drm/i915: Add PSR registers for PSR VLV/CHV Rodrigo Vivi
2014-11-06 18:17 ` R, Durgadoss
2014-11-14 0:34 ` Rodrigo Vivi
2014-10-28 18:45 ` [PATCH 02/10] drm/i915: VLV PSR: Status/enabled function Rodrigo Vivi
2014-11-03 12:30 ` Daniel Vetter
2014-11-06 18:25 ` R, Durgadoss
2014-11-07 9:28 ` Daniel Vetter
2014-10-28 18:45 ` [PATCH 03/10] drm/i915: Rename psr_do_exit/psr_exit Rodrigo Vivi
2014-10-28 18:45 ` [PATCH 04/10] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions Rodrigo Vivi
2014-11-06 18:32 ` R, Durgadoss
2014-11-14 0:33 ` Rodrigo Vivi
2014-11-14 10:02 ` Daniel Vetter [this message]
2014-10-28 18:45 ` [PATCH 05/10] drm/i915: PSR activate function Rodrigo Vivi
2014-10-28 18:45 ` [PATCH 06/10] drm/i915: VLV/CHV PSR Software timer mode control Rodrigo Vivi
2014-11-06 18:39 ` R, Durgadoss
2014-11-14 0:27 ` Rodrigo Vivi
2014-10-28 18:45 ` [PATCH 07/10] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR Rodrigo Vivi
2014-11-06 18:40 ` R, Durgadoss
2014-11-14 0:30 ` Rodrigo Vivi
2014-10-28 18:45 ` [PATCH 08/10] drm/i915: VLV/CHV PSR debugfs Rodrigo Vivi
2014-11-06 18:45 ` R, Durgadoss
2014-11-14 0:26 ` Rodrigo Vivi
2014-10-28 18:45 ` [PATCH 09/10] drm/i915: PSR Baytrail: Not available on Pipe C Rodrigo Vivi
2014-11-03 10:40 ` Imre Deak
2014-10-28 18:45 ` [PATCH 10/10] drm/i915: Enable PSR for Baytrail and Braswell Rodrigo Vivi
2014-11-06 18:49 ` R, Durgadoss
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