From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH] drm/i915: WaSetupGtModeTdRowDispatch:snb Date: Fri, 14 Nov 2014 13:13:16 +0200 Message-ID: <20141114111316.GA10649@intel.com> References: <1415953529-27850-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1415953529-27850-1-git-send-email-daniel.vetter@ffwll.ch> Sender: stable-owner@vger.kernel.org To: Daniel Vetter Cc: Intel Graphics Development , stable@vger.kernel.org, Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Fri, Nov 14, 2014 at 09:25:29AM +0100, Daniel Vetter wrote: > This reverts >=20 > commit 8d85d27281095e4df6eb97ae84326b5814337337 > Author: Ville Syrj=E4l=E4 > Date: Tue Feb 4 21:59:15 2014 +0200 >=20 > drm/i915: Fix SNB GT_MODE register setup I think you mean commit 6547fbdbfff62c99e4f7b4f985ff8b3454f33b0f Author: Daniel Vetter Date: Fri Dec 14 23:38:29 2012 +0100 drm/i915: Implement WaSetupGtModeTdRowDispatch >=20 > Reported-by: Leo Wolf > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D79996 > Cc: stable@vger.kernel.org > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_pm.c | 5 ----- > 1 file changed, 5 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/i= ntel_pm.c > index 9e87265f2448..03417a38cd09 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6472,11 +6472,6 @@ static void gen6_init_clock_gating(struct drm_= device *dev) > I915_WRITE(_3D_CHICKEN, > _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); > =20 > - /* WaSetupGtModeTdRowDispatch:snb */ > - if (IS_SNB_GT1(dev)) > - I915_WRITE(GEN6_GT_MODE, > - _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); > - > /* WaDisable_RenderCache_OperationalFlush:snb */ > I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > =20 > --=20 > 2.1.1 >=20 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx --=20 Ville Syrj=E4l=E4 Intel OTC