From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Daniel Vetter <daniel.vetter@intel.com>,
Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
stable@vger.kernel.org
Subject: Re: [PATCH] drm/i915: WaSetupGtModeTdRowDispatch:snb
Date: Fri, 14 Nov 2014 13:21:10 +0200 [thread overview]
Message-ID: <20141114112110.GB10649@intel.com> (raw)
In-Reply-To: <20141114111316.GA10649@intel.com>
On Fri, Nov 14, 2014 at 01:13:16PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 14, 2014 at 09:25:29AM +0100, Daniel Vetter wrote:
> > This reverts
> >
> > commit 8d85d27281095e4df6eb97ae84326b5814337337
> > Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Date: Tue Feb 4 21:59:15 2014 +0200
> >
> > drm/i915: Fix SNB GT_MODE register setup
>
> I think you mean
>
> commit 6547fbdbfff62c99e4f7b4f985ff8b3454f33b0f
> Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> Date: Fri Dec 14 23:38:29 2012 +0100
>
> drm/i915: Implement WaSetupGtModeTdRowDispatch
Oh, I guess functionally it reverts part of my patch since your original
patch was a nop due to the clear all bits part done later. Would be nice
to explain some of this in the commit message to avoid all sorts of
confusion.
>
> >
> > Reported-by: Leo Wolf <jclw@ymail.com>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79996
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 5 -----
> > 1 file changed, 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 9e87265f2448..03417a38cd09 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6472,11 +6472,6 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> > I915_WRITE(_3D_CHICKEN,
> > _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
> >
> > - /* WaSetupGtModeTdRowDispatch:snb */
> > - if (IS_SNB_GT1(dev))
> > - I915_WRITE(GEN6_GT_MODE,
> > - _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
> > -
> > /* WaDisable_RenderCache_OperationalFlush:snb */
> > I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
> >
> > --
> > 2.1.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
--
Ville Syrjälä
Intel OTC
_______________________________________________
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next prev parent reply other threads:[~2014-11-14 11:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-14 8:25 [PATCH] drm/i915: WaSetupGtModeTdRowDispatch:snb Daniel Vetter
2014-11-14 11:13 ` [Intel-gfx] " Ville Syrjälä
2014-11-14 11:21 ` Ville Syrjälä [this message]
2014-11-14 11:27 ` Jani Nikula
2014-11-14 14:25 ` shuang.he
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