From: Daniel Vetter <daniel@ffwll.ch>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 13/18] drm/i915: Store max cdclk value in dev_priv
Date: Mon, 17 Nov 2014 19:43:39 +0100 [thread overview]
Message-ID: <20141117184339.GI25711@phenom.ffwll.local> (raw)
In-Reply-To: <1416235432-16603-14-git-send-email-ville.syrjala@linux.intel.com>
On Mon, Nov 17, 2014 at 04:43:47PM +0200, ville.syrjala@linux.intel.com wrote:
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9c6bc82..5eeb456 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4745,6 +4745,21 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv)
> return vco_freq[hpll_freq] * 1000;
> }
>
> +static void intel_update_max_cdclk(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + if (IS_VALLEYVIEW(dev)) {
> + dev_priv->max_cdclk_freq = 400000;
I've thought the 400MHz mode is busted? Or is that just Punit bonghits on
SDVs and pre-prod boards?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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next prev parent reply other threads:[~2014-11-17 18:43 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-17 14:43 [PATCH 00/18] drm/i915: All sorts of cdclk stuff ville.syrjala
2014-11-17 14:43 ` [PATCH 01/18] drm/i915: Return more precise cdclk for gen2/3 ville.syrjala
2014-11-17 18:44 ` Daniel Vetter
2014-11-17 19:02 ` Ville Syrjälä
2014-11-17 19:13 ` Daniel Vetter
2014-11-17 14:43 ` [PATCH 02/18] drm/i915: Fix i855_get_display_clock_speed() ville.syrjala
2014-11-17 14:43 ` [PATCH 03/18] drm/i915: Fix 852GM/GMV cdclk ville.syrjala
2014-11-17 14:43 ` [PATCH 04/18] drm/i915: Add cdclk extraction for g33, 965gm and g4x ville.syrjala
2014-11-17 14:43 ` [PATCH 05/18] drm/i915: ILK cdclk seems to be 450MHz ville.syrjala
2014-11-17 14:43 ` [PATCH 06/18] drm/i915: Assume 400 MHz cdclk for the rest of gen4-7 ville.syrjala
2014-11-17 18:46 ` Daniel Vetter
2014-11-17 19:22 ` Ville Syrjälä
2014-11-17 14:43 ` [PATCH 07/18] drm/i915: Simplify ilk_get_aux_clock_divider() ville.syrjala
2014-11-17 14:43 ` [PATCH 08/18] drm/i915: Convert the ddi cdclk code to .get_display_clock_speed() ville.syrjala
2014-11-17 14:43 ` [PATCH 09/18] drm/i915: Warn when cdclk for the platforms is not known ville.syrjala
2014-11-17 14:43 ` [PATCH 10/18] drm/i915: Cache the current cdclk frequency in dev_priv ville.syrjala
2014-11-17 14:43 ` [PATCH 11/18] drm/i915: Use cached cdclk value ville.syrjala
2014-11-17 18:41 ` Daniel Vetter
2014-11-17 19:06 ` Ville Syrjälä
2014-11-17 19:09 ` Daniel Vetter
2014-11-17 14:43 ` [PATCH 12/18] drm/i915: Unify ilk and hsw .get_aux_clock_divider() ville.syrjala
2014-11-17 14:43 ` [PATCH 13/18] drm/i915: Store max cdclk value in dev_priv ville.syrjala
2014-11-17 18:43 ` Daniel Vetter [this message]
2014-11-17 19:30 ` Ville Syrjälä
2014-11-17 14:43 ` [PATCH 14/18] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk ville.syrjala
2014-11-17 19:02 ` Daniel Vetter
2014-11-18 0:38 ` Runyan, Arthur J
2014-11-17 14:43 ` [PATCH 15/18] drm/i915: Fix chv cdclk support ville.syrjala
2014-11-17 14:43 ` [PATCH 16/18] drm/i915: HSW cdclk change support ville.syrjala
2014-11-17 14:43 ` [PATCH 17/18] drm/i915: Add IS_BDW_ULX() ville.syrjala
2014-11-17 14:43 ` [PATCH 18/18] drm/i915: BDW cdclk change support ville.syrjala
2014-11-18 6:51 ` shuang.he
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