From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 11/18] drm/i915: Use cached cdclk value
Date: Mon, 17 Nov 2014 21:06:53 +0200 [thread overview]
Message-ID: <20141117190653.GM10649@intel.com> (raw)
In-Reply-To: <20141117184144.GH25711@phenom.ffwll.local>
On Mon, Nov 17, 2014 at 07:41:44PM +0100, Daniel Vetter wrote:
> On Mon, Nov 17, 2014 at 04:43:45PM +0200, ville.syrjala@linux.intel.com wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index d8841c7..d23aa05 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1401,6 +1401,6 @@ int i915_get_cdclk_freq(void)
> > dev_priv = container_of(hsw_pwr, struct drm_i915_private,
> > power_domains);
> >
> > - return dev_priv->display.get_display_clock_speed(dev_priv->dev);
> > + return dev_priv->cdclk_freq;
>
> Maybe this here is the reason why hsw shouldn't change cdclck - the audio
> side just falls over?
I must admit that I didn't check whether the audio side will query the
cdclk again after every mode change. It really should, but often reality
doesn't match my expectations :)
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-11-17 19:07 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-17 14:43 [PATCH 00/18] drm/i915: All sorts of cdclk stuff ville.syrjala
2014-11-17 14:43 ` [PATCH 01/18] drm/i915: Return more precise cdclk for gen2/3 ville.syrjala
2014-11-17 18:44 ` Daniel Vetter
2014-11-17 19:02 ` Ville Syrjälä
2014-11-17 19:13 ` Daniel Vetter
2014-11-17 14:43 ` [PATCH 02/18] drm/i915: Fix i855_get_display_clock_speed() ville.syrjala
2014-11-17 14:43 ` [PATCH 03/18] drm/i915: Fix 852GM/GMV cdclk ville.syrjala
2014-11-17 14:43 ` [PATCH 04/18] drm/i915: Add cdclk extraction for g33, 965gm and g4x ville.syrjala
2014-11-17 14:43 ` [PATCH 05/18] drm/i915: ILK cdclk seems to be 450MHz ville.syrjala
2014-11-17 14:43 ` [PATCH 06/18] drm/i915: Assume 400 MHz cdclk for the rest of gen4-7 ville.syrjala
2014-11-17 18:46 ` Daniel Vetter
2014-11-17 19:22 ` Ville Syrjälä
2014-11-17 14:43 ` [PATCH 07/18] drm/i915: Simplify ilk_get_aux_clock_divider() ville.syrjala
2014-11-17 14:43 ` [PATCH 08/18] drm/i915: Convert the ddi cdclk code to .get_display_clock_speed() ville.syrjala
2014-11-17 14:43 ` [PATCH 09/18] drm/i915: Warn when cdclk for the platforms is not known ville.syrjala
2014-11-17 14:43 ` [PATCH 10/18] drm/i915: Cache the current cdclk frequency in dev_priv ville.syrjala
2014-11-17 14:43 ` [PATCH 11/18] drm/i915: Use cached cdclk value ville.syrjala
2014-11-17 18:41 ` Daniel Vetter
2014-11-17 19:06 ` Ville Syrjälä [this message]
2014-11-17 19:09 ` Daniel Vetter
2014-11-17 14:43 ` [PATCH 12/18] drm/i915: Unify ilk and hsw .get_aux_clock_divider() ville.syrjala
2014-11-17 14:43 ` [PATCH 13/18] drm/i915: Store max cdclk value in dev_priv ville.syrjala
2014-11-17 18:43 ` Daniel Vetter
2014-11-17 19:30 ` Ville Syrjälä
2014-11-17 14:43 ` [PATCH 14/18] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk ville.syrjala
2014-11-17 19:02 ` Daniel Vetter
2014-11-18 0:38 ` Runyan, Arthur J
2014-11-17 14:43 ` [PATCH 15/18] drm/i915: Fix chv cdclk support ville.syrjala
2014-11-17 14:43 ` [PATCH 16/18] drm/i915: HSW cdclk change support ville.syrjala
2014-11-17 14:43 ` [PATCH 17/18] drm/i915: Add IS_BDW_ULX() ville.syrjala
2014-11-17 14:43 ` [PATCH 18/18] drm/i915: BDW cdclk change support ville.syrjala
2014-11-18 6:51 ` shuang.he
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20141117190653.GM10649@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=daniel@ffwll.ch \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox