Re: [PATCH 13/18] drm/i915: Store max cdclk value in dev_priv

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 13/18] drm/i915: Store max cdclk value in dev_priv
Date: Mon, 17 Nov 2014 21:30:23 +0200	[thread overview]
Message-ID: <20141117193023.GO10649@intel.com> (raw)
In-Reply-To: <20141117184339.GI25711@phenom.ffwll.local>

On Mon, Nov 17, 2014 at 07:43:39PM +0100, Daniel Vetter wrote:
> On Mon, Nov 17, 2014 at 04:43:47PM +0200, ville.syrjala@linux.intel.com wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 9c6bc82..5eeb456 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4745,6 +4745,21 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv)
> >  	return vco_freq[hpll_freq] * 1000;
> >  }
> >  
> > +static void intel_update_max_cdclk(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	if (IS_VALLEYVIEW(dev)) {
> > +		dev_priv->max_cdclk_freq = 400000;
> 
> I've thought the 400MHz mode is busted? Or is that just Punit bonghits on
> SDVs and pre-prod boards?

AFAIK it should work. It's just that the Punit doesn't actually support
it, so we have to bypass the Punit and poke at CCK directly to get
there.

-- 
Ville Syrjälä
Intel OTC
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