From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: clinton.a.taylor@intel.com
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C
Date: Wed, 3 Dec 2014 23:01:12 +0200 [thread overview]
Message-ID: <20141203210112.GZ10649@intel.com> (raw)
In-Reply-To: <1417630230-3171-1-git-send-email-clinton.a.taylor@intel.com>
On Wed, Dec 03, 2014 at 10:10:30AM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Added PIPE C register support for CHV audio programming.
nak. The offset between the pipes looks constant so it should work
just fine with _PIPE().
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc03fac..3d5813a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6189,14 +6189,18 @@ enum punit_power_well {
>
> #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
> #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
> -#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
> +#define _CHV_HDMIW_HDMIEDID_C (VLV_DISPLAY_BASE + 0x62250)
> +#define VLV_HDMIW_HDMIEDID(pipe) _PIPE3(pipe, \
> _VLV_HDMIW_HDMIEDID_A, \
> - _VLV_HDMIW_HDMIEDID_B)
> + _VLV_HDMIW_HDMIEDID_B, \
> + _CHV_HDMIW_HDMIEDID_C)
> #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
> #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
> -#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
> +#define _CHV_AUD_CNTL_ST_C (VLV_DISPLAY_BASE + 0x622B4)
> +#define VLV_AUD_CNTL_ST(pipe) _PIPE3(pipe, \
> _VLV_AUD_CNTL_ST_A, \
> - _VLV_AUD_CNTL_ST_B)
> + _VLV_AUD_CNTL_ST_B, \
> + _CHV_AUD_CNTL_ST_C)
> #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
>
> /* These are the 4 32-bit write offset registers for each stream
> @@ -6217,9 +6221,11 @@ enum punit_power_well {
> _CPT_AUD_CONFIG_B)
> #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
> #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
> -#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
> +#define _CHV_AUD_CONFIG_C (VLV_DISPLAY_BASE + 0x62200)
> +#define VLV_AUD_CFG(pipe) _PIPE3(pipe, \
> _VLV_AUD_CONFIG_A, \
> - _VLV_AUD_CONFIG_B)
> + _VLV_AUD_CONFIG_B, \
> + _CHV_AUD_CONFIG_C)
>
> #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
> #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-12-03 21:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-03 18:10 [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C clinton.a.taylor
2014-12-03 21:01 ` Ville Syrjälä [this message]
2014-12-03 21:09 ` Clint Taylor
2014-12-04 8:41 ` Jani Nikula
2014-12-04 19:08 ` Clint Taylor
2014-12-04 22:21 ` Clint Taylor
2014-12-05 8:37 ` Jani Nikula
2014-12-05 11:42 ` Imre Deak
2014-12-05 11:57 ` Jani Nikula
2014-12-05 13:23 ` Imre Deak
2014-12-05 14:27 ` Daniel Vetter
2014-12-05 23:30 ` Clint Taylor
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