* [PATCH] drm/i915/chv: Add additional workarounds for CHV
@ 2014-12-03 19:15 Arun Siluvery
2014-12-04 10:58 ` Ville Syrjälä
2014-12-05 1:10 ` shuang.he
0 siblings, 2 replies; 4+ messages in thread
From: Arun Siluvery @ 2014-12-03 19:15 UTC (permalink / raw)
To: intel-gfx
These w/a were recently identified while debugging another issue,
+WaClearFlowControlGpgpuContextSave:chv
+Wa4x4STCOptimizationDisable:chv
For: VIZ-4090
Change-Id: I08d2176dec609396c3a7c2e48b2413e233799fc4
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc03fac..7c7663f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6131,6 +6131,7 @@ enum punit_power_well {
#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
#define GEN8_ROW_CHICKEN 0xe4f0
+#define FLOW_CONTROL_ENABLE (1<<15)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
#define STALL_DOP_GATING_DISABLE (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 79b4ca5..525c9bf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -796,8 +796,10 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
/* WaDisablePartialInstShootdown:chv */
/* WaDisableThreadStallDopClockGating:chv */
+ /* WaClearFlowControlGpgpuContextSave:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
+ FLOW_CONTROL_ENABLE |
STALL_DOP_GATING_DISABLE);
/* Use Force Non-Coherent whenever executing a 3D context. This is a
@@ -810,6 +812,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
HDC_FORCE_NON_COHERENT |
HDC_DONOT_FETCH_MEM_WHEN_MASKED);
+ /* Wa4x4STCOptimizationDisable:chv */
+ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
+
return 0;
}
--
2.1.2
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/chv: Add additional workarounds for CHV
2014-12-03 19:15 [PATCH] drm/i915/chv: Add additional workarounds for CHV Arun Siluvery
@ 2014-12-04 10:58 ` Ville Syrjälä
2014-12-04 11:12 ` Daniel Vetter
2014-12-05 1:10 ` shuang.he
1 sibling, 1 reply; 4+ messages in thread
From: Ville Syrjälä @ 2014-12-04 10:58 UTC (permalink / raw)
To: Arun Siluvery; +Cc: intel-gfx
On Wed, Dec 03, 2014 at 07:15:31PM +0000, Arun Siluvery wrote:
> These w/a were recently identified while debugging another issue,
> +WaClearFlowControlGpgpuContextSave:chv
> +Wa4x4STCOptimizationDisable:chv
>
> For: VIZ-4090
> Change-Id: I08d2176dec609396c3a7c2e48b2413e233799fc4
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc03fac..7c7663f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6131,6 +6131,7 @@ enum punit_power_well {
> #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
>
> #define GEN8_ROW_CHICKEN 0xe4f0
> +#define FLOW_CONTROL_ENABLE (1<<15)
> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
> #define STALL_DOP_GATING_DISABLE (1<<5)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 79b4ca5..525c9bf 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -796,8 +796,10 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>
> /* WaDisablePartialInstShootdown:chv */
> /* WaDisableThreadStallDopClockGating:chv */
> + /* WaClearFlowControlGpgpuContextSave:chv */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> + FLOW_CONTROL_ENABLE |
This seems to be the default value already. I suppose there's no real
harm in setting it though, but then we should also do the same for BDW.
Would be nice if we actually did a GPU reset on driver load to guarantee
a more consistent initial state...
> STALL_DOP_GATING_DISABLE);
>
> /* Use Force Non-Coherent whenever executing a 3D context. This is a
> @@ -810,6 +812,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> HDC_FORCE_NON_COHERENT |
> HDC_DONOT_FETCH_MEM_WHEN_MASKED);
>
> + /* Wa4x4STCOptimizationDisable:chv */
> + WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
> +
> return 0;
> }
>
> --
> 2.1.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/chv: Add additional workarounds for CHV
2014-12-04 10:58 ` Ville Syrjälä
@ 2014-12-04 11:12 ` Daniel Vetter
0 siblings, 0 replies; 4+ messages in thread
From: Daniel Vetter @ 2014-12-04 11:12 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Dec 04, 2014 at 12:58:40PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 03, 2014 at 07:15:31PM +0000, Arun Siluvery wrote:
> > These w/a were recently identified while debugging another issue,
> > +WaClearFlowControlGpgpuContextSave:chv
> > +Wa4x4STCOptimizationDisable:chv
> >
> > For: VIZ-4090
> > Change-Id: I08d2176dec609396c3a7c2e48b2413e233799fc4
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index dc03fac..7c7663f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6131,6 +6131,7 @@ enum punit_power_well {
> > #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
> >
> > #define GEN8_ROW_CHICKEN 0xe4f0
> > +#define FLOW_CONTROL_ENABLE (1<<15)
> > #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
> > #define STALL_DOP_GATING_DISABLE (1<<5)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 79b4ca5..525c9bf 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -796,8 +796,10 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> >
> > /* WaDisablePartialInstShootdown:chv */
> > /* WaDisableThreadStallDopClockGating:chv */
> > + /* WaClearFlowControlGpgpuContextSave:chv */
> > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> > + FLOW_CONTROL_ENABLE |
>
> This seems to be the default value already. I suppose there's no real
> harm in setting it though, but then we should also do the same for BDW.
>
> Would be nice if we actually did a GPU reset on driver load to guarantee
> a more consistent initial state...
We have some half-baked testcase to compare the different wa registers
states after driver load, reset and suspend/resume. But that's not yet
been fixed up to also take all the static wa settings into account.
Would be awesome if that would finally happen.
/me dreaming ;-)
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/chv: Add additional workarounds for CHV
2014-12-03 19:15 [PATCH] drm/i915/chv: Add additional workarounds for CHV Arun Siluvery
2014-12-04 10:58 ` Ville Syrjälä
@ 2014-12-05 1:10 ` shuang.he
1 sibling, 0 replies; 4+ messages in thread
From: shuang.he @ 2014-12-05 1:10 UTC (permalink / raw)
To: shuang.he, intel-gfx, arun.siluvery
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK -2 366/366 364/366
SNB 450/450 450/450
IVB +16 481/498 497/498
BYT 289/289 289/289
HSW 564/564 564/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*ILK igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible PASS(2, M37M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_bcs-flip-vs-modeset-interruptible PASS(3, M37M26) DMESG_WARN(1, M26)
IVB igt_kms_3d DMESG_WARN(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-128x128-onscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-128x128-random NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-128x128-sliding NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-256x256-offscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-256x256-onscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-256x256-sliding NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-64x64-offscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-64x64-onscreen NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
*IVB igt_kms_cursor_crc_cursor-64x64-random NSPT(1, M34)PASS(10, M4M34M21) DMESG_WARN(1, M21)
IVB igt_kms_cursor_crc_cursor-64x64-sliding NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_cursor_crc_cursor-size-change NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_fence_pin_leak NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_rotation_crc_primary-rotation NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
IVB igt_kms_rotation_crc_sprite-rotation NSPT(1, M34)PASS(10, M4M34M21) PASS(1, M21)
Note: You need to pay more attention to line start with '*'
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2014-12-03 19:15 [PATCH] drm/i915/chv: Add additional workarounds for CHV Arun Siluvery
2014-12-04 10:58 ` Ville Syrjälä
2014-12-04 11:12 ` Daniel Vetter
2014-12-05 1:10 ` shuang.he
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