* [PATCH] drm/i915: Forcewake Register Range changes for CHV
@ 2014-12-11 7:18 deepak.s
2014-12-10 14:31 ` Ville Syrjälä
0 siblings, 1 reply; 5+ messages in thread
From: deepak.s @ 2014-12-11 7:18 UTC (permalink / raw)
To: intel-gfx; +Cc: daniel.vetter
From: Deepak S <deepak.s@linux.intel.com>
According to updated BSpec, Render/Common Wells register range changed.
Updating the same to match the spec and avoid extra forcewake for none
forcewake range.
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 46de8d7..dd36f9b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -647,9 +647,9 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
(REG_RANGE((reg), 0x2000, 0x4000) || \
- REG_RANGE((reg), 0x5000, 0x8000) || \
+ REG_RANGE((reg), 0x5200, 0x8000) || \
REG_RANGE((reg), 0x8300, 0x8500) || \
- REG_RANGE((reg), 0xB000, 0xC000) || \
+ REG_RANGE((reg), 0xB000, 0xB480) || \
REG_RANGE((reg), 0xE000, 0xE800))
#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
@@ -665,10 +665,7 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
REG_RANGE((reg), 0x8000, 0x8300) || \
REG_RANGE((reg), 0x8500, 0x8600) || \
REG_RANGE((reg), 0x9000, 0xB000) || \
- REG_RANGE((reg), 0xC000, 0xC800) || \
- REG_RANGE((reg), 0xF000, 0x10000) || \
- REG_RANGE((reg), 0x14000, 0x14400) || \
- REG_RANGE((reg), 0x22000, 0x24000))
+ REG_RANGE((reg), 0xF000, 0x10000))
#define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
REG_RANGE((reg), 0xB00, 0x2000)
--
1.9.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Forcewake Register Range changes for CHV
2014-12-11 7:18 [PATCH] drm/i915: Forcewake Register Range changes for CHV deepak.s
@ 2014-12-10 14:31 ` Ville Syrjälä
2014-12-11 16:04 ` Deepak S
0 siblings, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2014-12-10 14:31 UTC (permalink / raw)
To: deepak.s; +Cc: daniel.vetter, intel-gfx
On Thu, Dec 11, 2014 at 12:48:41PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> According to updated BSpec, Render/Common Wells register range changed.
> Updating the same to match the spec and avoid extra forcewake for none
> forcewake range.
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 9 +++------
> 1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 46de8d7..dd36f9b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -647,9 +647,9 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
>
> #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
> (REG_RANGE((reg), 0x2000, 0x4000) || \
> - REG_RANGE((reg), 0x5000, 0x8000) || \
> + REG_RANGE((reg), 0x5200, 0x8000) || \
> REG_RANGE((reg), 0x8300, 0x8500) || \
> - REG_RANGE((reg), 0xB000, 0xC000) || \
> + REG_RANGE((reg), 0xB000, 0xB480) || \
> REG_RANGE((reg), 0xE000, 0xE800))
>
> #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
> @@ -665,10 +665,7 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
> REG_RANGE((reg), 0x8000, 0x8300) || \
> REG_RANGE((reg), 0x8500, 0x8600) || \
> REG_RANGE((reg), 0x9000, 0xB000) || \
> - REG_RANGE((reg), 0xC000, 0xC800) || \
> - REG_RANGE((reg), 0xF000, 0x10000) || \
> - REG_RANGE((reg), 0x14000, 0x14400) || \
> - REG_RANGE((reg), 0x22000, 0x24000))
> + REG_RANGE((reg), 0xF000, 0x10000))
Looks correct.
It looks like the media offsets could use a small adjustment as well:
- REG_RANGE((reg), 0x30000, 0x40000)
+ REG_RANGE((reg), 0x30000, 0x38000)
So with that changed
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
One thing I don't understand though; Why is the [0x100000,0x180000[ range
marked as GWK in the spreadsheet? That's where the forcewake req/ack
registers live as well as some other GTFIFO stuff etc. How can you take
forcewake if the forcewake req/ack itself would need forcewake. I think
this must be an error in the spreadsheet and that range should be GNW.
>
> #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
> REG_RANGE((reg), 0xB00, 0x2000)
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Forcewake Register Range changes for CHV
2014-12-10 14:31 ` Ville Syrjälä
@ 2014-12-11 16:04 ` Deepak S
2014-12-11 16:12 ` [PATCH v2] " deepak.s
0 siblings, 1 reply; 5+ messages in thread
From: Deepak S @ 2014-12-11 16:04 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: daniel.vetter, intel-gfx
On Wednesday 10 December 2014 08:01 PM, Ville Syrjälä wrote:
> On Thu, Dec 11, 2014 at 12:48:41PM +0530, deepak.s@linux.intel.com wrote:
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> According to updated BSpec, Render/Common Wells register range changed.
>> Updating the same to match the spec and avoid extra forcewake for none
>> forcewake range.
>>
>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_uncore.c | 9 +++------
>> 1 file changed, 3 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 46de8d7..dd36f9b 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -647,9 +647,9 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
>>
>> #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
>> (REG_RANGE((reg), 0x2000, 0x4000) || \
>> - REG_RANGE((reg), 0x5000, 0x8000) || \
>> + REG_RANGE((reg), 0x5200, 0x8000) || \
>> REG_RANGE((reg), 0x8300, 0x8500) || \
>> - REG_RANGE((reg), 0xB000, 0xC000) || \
>> + REG_RANGE((reg), 0xB000, 0xB480) || \
>> REG_RANGE((reg), 0xE000, 0xE800))
>>
>> #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
>> @@ -665,10 +665,7 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
>> REG_RANGE((reg), 0x8000, 0x8300) || \
>> REG_RANGE((reg), 0x8500, 0x8600) || \
>> REG_RANGE((reg), 0x9000, 0xB000) || \
>> - REG_RANGE((reg), 0xC000, 0xC800) || \
>> - REG_RANGE((reg), 0xF000, 0x10000) || \
>> - REG_RANGE((reg), 0x14000, 0x14400) || \
>> - REG_RANGE((reg), 0x22000, 0x24000))
>> + REG_RANGE((reg), 0xF000, 0x10000))
> Looks correct.
>
> It looks like the media offsets could use a small adjustment as well:
> - REG_RANGE((reg), 0x30000, 0x40000)
> + REG_RANGE((reg), 0x30000, 0x38000)
>
> So with that changed
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks for reviewing...
> One thing I don't understand though; Why is the [0x100000,0x180000[ range
> marked as GWK in the spreadsheet? That's where the forcewake req/ack
> registers live as well as some other GTFIFO stuff etc. How can you take
> forcewake if the forcewake req/ack itself would need forcewake. I think
> this must be an error in the spreadsheet and that range should be GNW.
I think [0x100000,0x180000] is already above the forecewake range [0x40000]. We need request for a spec update.
It should be GNK
>>
>> #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
>> REG_RANGE((reg), 0xB00, 0x2000)
>> --
>> 1.9.1
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] drm/i915: Forcewake Register Range changes for CHV
2014-12-11 16:04 ` Deepak S
@ 2014-12-11 16:12 ` deepak.s
2014-12-10 17:02 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: deepak.s @ 2014-12-11 16:12 UTC (permalink / raw)
To: intel-gfx; +Cc: daniel.vetter
From: Deepak S <deepak.s@linux.intel.com>
According to updated BSpec, Render/Common/media Wells register range changed.
Updating the same to match the spec and avoid extra forcewake for none
forcewake range.
v2: Update media forcewake range (Ville)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 46de8d7..ffdd042 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -647,9 +647,9 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
(REG_RANGE((reg), 0x2000, 0x4000) || \
- REG_RANGE((reg), 0x5000, 0x8000) || \
+ REG_RANGE((reg), 0x5200, 0x8000) || \
REG_RANGE((reg), 0x8300, 0x8500) || \
- REG_RANGE((reg), 0xB000, 0xC000) || \
+ REG_RANGE((reg), 0xB000, 0xB480) || \
REG_RANGE((reg), 0xE000, 0xE800))
#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
@@ -658,17 +658,14 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
REG_RANGE((reg), 0x12000, 0x14000) || \
REG_RANGE((reg), 0x1A000, 0x1C000) || \
REG_RANGE((reg), 0x1E800, 0x1EA00) || \
- REG_RANGE((reg), 0x30000, 0x40000))
+ REG_RANGE((reg), 0x30000, 0x38000))
#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
(REG_RANGE((reg), 0x4000, 0x5000) || \
REG_RANGE((reg), 0x8000, 0x8300) || \
REG_RANGE((reg), 0x8500, 0x8600) || \
REG_RANGE((reg), 0x9000, 0xB000) || \
- REG_RANGE((reg), 0xC000, 0xC800) || \
- REG_RANGE((reg), 0xF000, 0x10000) || \
- REG_RANGE((reg), 0x14000, 0x14400) || \
- REG_RANGE((reg), 0x22000, 0x24000))
+ REG_RANGE((reg), 0xF000, 0x10000))
#define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
REG_RANGE((reg), 0xB00, 0x2000)
--
1.9.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/i915: Forcewake Register Range changes for CHV
2014-12-11 16:12 ` [PATCH v2] " deepak.s
@ 2014-12-10 17:02 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2014-12-10 17:02 UTC (permalink / raw)
To: deepak.s; +Cc: daniel.vetter, intel-gfx
On Thu, Dec 11, 2014 at 09:42:49PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> According to updated BSpec, Render/Common/media Wells register range changed.
> Updating the same to match the spec and avoid extra forcewake for none
> forcewake range.
>
> v2: Update media forcewake range (Ville)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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2014-12-11 7:18 [PATCH] drm/i915: Forcewake Register Range changes for CHV deepak.s
2014-12-10 14:31 ` Ville Syrjälä
2014-12-11 16:04 ` Deepak S
2014-12-11 16:12 ` [PATCH v2] " deepak.s
2014-12-10 17:02 ` Daniel Vetter
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