From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force the CS stall for invalidate flushes Date: Fri, 12 Dec 2014 11:09:15 +0200 Message-ID: <20141212090915.GL10649@intel.com> References: <1418285821-12868-1-git-send-email-chris@chris-wilson.co.uk> <1418285821-12868-2-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1418285821-12868-2-git-send-email-chris@chris-wilson.co.uk> Sender: stable-owner@vger.kernel.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org, Simon Farnsworth , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Dec 11, 2014 at 08:17:00AM +0000, Chris Wilson wrote: > In order to act as a full command barrier by itself, we need to tell = the > pipecontrol to actually stall the command streamer while the flush ru= ns. > We require the full command barrier before operations like > MI_SET_CONTEXT, which currently rely on a prior invalidate flush. >=20 > References: https://bugs.freedesktop.org/show_bug.cgi?id=3D83677 > Cc: Simon Farnsworth > Signed-off-by: Chris Wilson > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/dr= m/i915/intel_ringbuffer.c > index 282279b83ca4..02fb478a2867 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -380,6 +380,8 @@ gen7_render_ring_flush(struct intel_engine_cs *ri= ng, > flags |=3D PIPE_CONTROL_QW_WRITE; > flags |=3D PIPE_CONTROL_GLOBAL_GTT_IVB; > =20 > + flags |=3D PIPE_CONTROL_STALL_AT_SCOREBOARD; > + Hmm. BSpec says that the render cache won't be flushed when this bit is set. Is that going to cause problems for the gpu_cache_dirty cases where seem to do invalidate+flush with a single PIPE_CONTROL? > /* Workaround: we must issue a pipe_control with CS-stall bit > * set before a pipe_control command that has the state cache > * invalidate bit set. */ > --=20 > 2.1.3 >=20 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx --=20 Ville Syrj=E4l=E4 Intel OTC