From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force the CS stall for invalidate flushes Date: Fri, 12 Dec 2014 13:29:13 +0200 Message-ID: <20141212112913.GP10649@intel.com> References: <1418285821-12868-1-git-send-email-chris@chris-wilson.co.uk> <1418285821-12868-2-git-send-email-chris@chris-wilson.co.uk> <20141212090915.GL10649@intel.com> <20141212092049.GF22904@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <20141212092049.GF22904@nuc-i3427.alporthouse.com> Sender: stable-owner@vger.kernel.org To: Chris Wilson , intel-gfx@lists.freedesktop.org, Simon Farnsworth , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Dec 12, 2014 at 09:20:49AM +0000, Chris Wilson wrote: > On Fri, Dec 12, 2014 at 11:09:15AM +0200, Ville Syrj=E4l=E4 wrote: > > On Thu, Dec 11, 2014 at 08:17:00AM +0000, Chris Wilson wrote: > > > In order to act as a full command barrier by itself, we need to t= ell the > > > pipecontrol to actually stall the command streamer while the flus= h runs. > > > We require the full command barrier before operations like > > > MI_SET_CONTEXT, which currently rely on a prior invalidate flush. > > >=20 > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=3D83677 > > > Cc: Simon Farnsworth > > > Signed-off-by: Chris Wilson > > > Cc: stable@vger.kernel.org > > > --- > > > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ > > > 1 file changed, 2 insertions(+) > > >=20 > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gp= u/drm/i915/intel_ringbuffer.c > > > index 282279b83ca4..02fb478a2867 100644 > > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > > @@ -380,6 +380,8 @@ gen7_render_ring_flush(struct intel_engine_cs= *ring, > > > flags |=3D PIPE_CONTROL_QW_WRITE; > > > flags |=3D PIPE_CONTROL_GLOBAL_GTT_IVB; > > > =20 > > > + flags |=3D PIPE_CONTROL_STALL_AT_SCOREBOARD; > > > + > >=20 > > Hmm. BSpec says that the render cache won't be flushed when this bi= t > > is set. Is that going to cause problems for the gpu_cache_dirty cas= es > > where seem to do invalidate+flush with a single PIPE_CONTROL? >=20 > I thought it was DEPTH_STALL that disabled the write flush. Hmm. Yeah, the previous sentence talks about the depth stall bit. So I suppose it could still be referring to the depth stall bit when it says the render cache flush won't be flushed. > It is > redundant in the case where the write flush is taking place though an= d > you can do: >=20 > /* bspec is not entirely clear when the render target cache flush is > * disabled with other stall bits set, so don't set any additional > * stalls if we are already using the cache flush. > */ > if ((flags & PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH) =3D=3D 0) > flags |=3D PIPE_CONTROL_STALL_AT_SCOREBOARD; > -Chris >=20 > --=20 > Chris Wilson, Intel Open Source Technology Centre --=20 Ville Syrj=E4l=E4 Intel OTC