From: Ben Widawsky <ben@bwidawsk.net>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Ben Widawsky <benjamin.widawsky@intel.com>
Subject: Re: [PATCH 4/4] drm/i915: Opportunistically reduce flushing at execbuf
Date: Sun, 14 Dec 2014 15:37:36 -0800 [thread overview]
Message-ID: <20141214233735.GA1497@bwidawsk.net> (raw)
In-Reply-To: <20141214131221.GD10649@intel.com>
On Sun, Dec 14, 2014 at 03:12:21PM +0200, Ville Syrjälä wrote:
> On Sat, Dec 13, 2014 at 07:08:24PM -0800, Ben Widawsky wrote:
> > If we're moving a bunch of buffers from the CPU domain to the GPU domain, and
> > we've already blown out the entire cache via a wbinvd, there is nothing more to
> > do.
> >
> > With this and the previous patches, I am seeing a 3x FPS increase on a certain
> > benchmark which uses a giant 2d array texture. Unless I missed something in the
> > code, it should only effect non-LLC i915 platforms.
> >
> > I haven't yet run any numbers for other benchmarks, nor have I attempted to
> > check if various conformance tests still pass.
> >
> > NOTE: As mentioned in the previous patch, if one can easily obtain the largest
> > buffer and attempt to flush it first, the results would be even more desirable.
>
> So even with that optimization if you only have tons of small buffers
> that need to be flushed you'd still take the clflush path for every
> single one.
>
> How difficult would it to calculate the total size to be flushed first,
> and then make the clflush vs. wbinvd decision base on that?
>
I'll write the patch and send it to Eero for test.
It's not hard, and I think that's a good idea as well. One reason I didn't put
such code in this series is that moves away from a global DRM solution (and like
I said in the cover-letter, I am fine with that). Implementing this, I think in
the i915 code we'd just iterate through the BOs until we got to a certain
threshold, then just call wbinvd() from i915 and not even both with drm_cache.
You could also maybe try to shorcut if there are more than X buffers.
However, for what you describe, I think it might make more sense to let
userspace specify an execbuf flag to do the wbinvd(). Userspace can trivially
determine such info, it prevents having to iterate through the buffers an extra
time in the kernel.
I wonder if the clflushing many small objects is showing up on profiles? So far,
this specific microbenchmark was the only profile I'd seen where the clflushes
show up.
Thanks.
[snip]
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next prev parent reply other threads:[~2014-12-14 23:37 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1418526504-26316-1-git-send-email-benjamin.widawsky@intel.com>
2014-12-14 3:08 ` [PATCH 1/4] drm/cache: Use wbinvd helpers Ben Widawsky
2014-12-14 12:43 ` Chris Wilson
2014-12-15 7:49 ` Daniel Vetter
2014-12-15 20:26 ` [PATCH] [v2] " Ben Widawsky
2014-12-16 2:26 ` shuang.he
2014-12-16 7:56 ` Daniel Vetter
2014-12-14 3:08 ` [PATCH 2/4] drm/cache: Try to be smarter about clflushing on x86 Ben Widawsky
2014-12-14 4:15 ` Matt Turner
2014-12-15 22:07 ` Ben Widawsky
2014-12-14 12:59 ` [Intel-gfx] " Chris Wilson
2014-12-15 4:06 ` Jesse Barnes
2014-12-15 19:54 ` Ben Widawsky
2014-12-14 3:08 ` [PATCH 3/4] drm/cache: Return what type of cache flush occurred Ben Widawsky
2014-12-14 3:08 ` [PATCH 4/4] drm/i915: Opportunistically reduce flushing at execbuf Ben Widawsky
2014-12-14 9:35 ` shuang.he
2014-12-14 13:12 ` [Intel-gfx] " Ville Syrjälä
2014-12-14 23:37 ` Ben Widawsky [this message]
2014-12-15 7:55 ` Daniel Vetter
2014-12-15 8:20 ` Chris Wilson
2014-12-15 19:56 ` Ben Widawsky
2014-12-15 20:39 ` Chris Wilson
2014-12-15 21:06 ` [Intel-gfx] " Ben Widawsky
2014-12-16 7:57 ` Chris Wilson
2014-12-16 19:38 ` Ben Widawsky
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