* [PATCH 1/8] drm/i915: Rename struct intel_crtc_config to intel_crtc_state
2014-12-11 12:38 [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync Ander Conselvan de Oliveira
@ 2014-12-11 12:38 ` Ander Conselvan de Oliveira
2014-12-11 12:38 ` [PATCH 2/8] drm/i915: Embedded struct drm_crtc_state in intel_crtc_state Ander Conselvan de Oliveira
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-11 12:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, shuang.he
The objective is to make this structure usable with the atomic helpers,
so let's start with the rename. Patch generated with coccinelle:
@@ @@
-struct intel_crtc_config
+struct intel_crtc_state
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/intel_crt.c | 6 +--
drivers/gpu/drm/i915/intel_ddi.c | 10 ++--
drivers/gpu/drm/i915/intel_display.c | 100 +++++++++++++++++------------------
drivers/gpu/drm/i915/intel_dp.c | 12 ++---
drivers/gpu/drm/i915/intel_dp_mst.c | 4 +-
drivers/gpu/drm/i915/intel_drv.h | 28 +++++-----
drivers/gpu/drm/i915/intel_dsi.c | 4 +-
drivers/gpu/drm/i915/intel_dvo.c | 6 +--
drivers/gpu/drm/i915/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/intel_panel.c | 8 +--
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_sdvo.c | 6 +--
drivers/gpu/drm/i915/intel_tv.c | 4 +-
15 files changed, 101 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11e85cb..7d60d38 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -458,7 +458,7 @@ struct drm_i915_error_state {
struct intel_connector;
struct intel_encoder;
-struct intel_crtc_config;
+struct intel_crtc_state;
struct intel_plane_config;
struct intel_crtc;
struct intel_limit;
@@ -497,7 +497,7 @@ struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
- struct intel_crtc_config *);
+ struct intel_crtc_state *);
void (*get_plane_config)(struct intel_crtc *,
struct intel_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index a9af9a4..675b85a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -110,7 +110,7 @@ static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
}
static void intel_crt_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = encoder->base.dev;
int dotclock;
@@ -126,7 +126,7 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
}
static void hsw_crt_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
intel_ddi_get_config(encoder, pipe_config);
@@ -303,7 +303,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
}
static bool intel_crt_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = encoder->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4e2e860..9d69b61 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -732,7 +732,7 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
static void skl_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
int link_clock = 0;
@@ -776,7 +776,7 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
}
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
int link_clock = 0;
@@ -832,7 +832,7 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
}
void intel_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
hsw_ddi_clock_get(encoder, pipe_config);
}
@@ -2022,7 +2022,7 @@ static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
}
void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
@@ -2119,7 +2119,7 @@ static void intel_ddi_destroy(struct drm_encoder *encoder)
}
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
int type = encoder->type;
int port = intel_ddi_get_encoder_port(encoder);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a9bdc12..0b1a0af 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -76,9 +76,9 @@ static const uint32_t intel_cursor_formats[] = {
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
int x, int y, struct drm_framebuffer *old_fb);
@@ -95,9 +95,9 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipeconf(struct drm_crtc *crtc);
static void intel_set_pipe_csc(struct drm_crtc *crtc);
static void vlv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_config *pipe_config);
+ const struct intel_crtc_state *pipe_config);
static void chv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_config *pipe_config);
+ const struct intel_crtc_state *pipe_config);
static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
{
@@ -1505,7 +1505,7 @@ static void intel_init_dpio(struct drm_device *dev)
}
static void vlv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_config *pipe_config)
+ const struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1544,7 +1544,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
}
static void chv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_config *pipe_config)
+ const struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4599,7 +4599,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc_config *pipe_config = &crtc->config;
+ struct intel_crtc_state *pipe_config = &crtc->config;
if (!crtc->config.gmch_pfit.control)
return;
@@ -5364,7 +5364,7 @@ bool intel_connector_get_hw_state(struct intel_connector *connector)
}
static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *pipe_B_crtc =
@@ -5423,7 +5423,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
#define RETRY 1
static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = intel_crtc->base.dev;
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
@@ -5469,7 +5469,7 @@ retry:
}
static void hsw_compute_ips_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
pipe_config->ips_enabled = i915.enable_ips &&
hsw_crtc_supports_ips(crtc) &&
@@ -5477,7 +5477,7 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
}
static int intel_crtc_compute_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5839,7 +5839,7 @@ void intel_dp_set_m_n(struct intel_crtc *crtc)
}
static void vlv_update_pll(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
u32 dpll, dpll_md;
@@ -5862,7 +5862,7 @@ static void vlv_update_pll(struct intel_crtc *crtc,
}
static void vlv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_config *pipe_config)
+ const struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5953,7 +5953,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
}
static void chv_update_pll(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
@@ -5966,7 +5966,7 @@ static void chv_update_pll(struct intel_crtc *crtc,
}
static void chv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_config *pipe_config)
+ const struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6051,7 +6051,7 @@ void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
{
struct intel_crtc *crtc =
to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
- struct intel_crtc_config pipe_config = {
+ struct intel_crtc_state pipe_config = {
.pixel_multiplier = 1,
.dpll = *dpll,
};
@@ -6266,7 +6266,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
}
static void intel_get_pipe_timings(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6308,7 +6308,7 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
}
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
@@ -6478,7 +6478,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
}
static void i9xx_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6508,7 +6508,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
}
static void vlv_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6599,7 +6599,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
}
static void chv_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6629,7 +6629,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
}
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7531,7 +7531,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
}
void intel_dp_get_m_n(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
if (crtc->config.has_pch_encoder)
intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
@@ -7542,14 +7542,14 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
}
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
&pipe_config->fdi_m_n, NULL);
}
static void skylake_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7565,7 +7565,7 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
}
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7649,7 +7649,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
}
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7979,7 +7979,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
enum port port,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
u32 temp, dpll_ctl1;
@@ -8010,7 +8010,7 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
enum port port,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
@@ -8025,7 +8025,7 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
}
static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8067,7 +8067,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
}
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8649,7 +8649,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
}
static int i9xx_pll_refclk(struct drm_device *dev,
- const struct intel_crtc_config *pipe_config)
+ const struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 dpll = pipe_config->dpll_hw_state.dpll;
@@ -8666,7 +8666,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
/* Returns the clock of the currently programmed mode of the given pipe. */
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8773,7 +8773,7 @@ int intel_dotclock_calculate(int link_freq,
}
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
@@ -8799,7 +8799,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
struct drm_display_mode *mode;
- struct intel_crtc_config pipe_config;
+ struct intel_crtc_state pipe_config;
int htot = I915_READ(HTOTAL(cpu_transcoder));
int hsync = I915_READ(HSYNC(cpu_transcoder));
int vtot = I915_READ(VTOTAL(cpu_transcoder));
@@ -9855,7 +9855,7 @@ static void intel_modeset_commit_output_state(struct drm_device *dev)
static void
connected_sink_compute_bpp(struct intel_connector *connector,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
int bpp = pipe_config->pipe_bpp;
@@ -9882,7 +9882,7 @@ connected_sink_compute_bpp(struct intel_connector *connector,
static int
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
struct drm_framebuffer *fb,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct intel_connector *connector;
@@ -9951,7 +9951,7 @@ static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
}
static void intel_dump_pipe_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config,
+ struct intel_crtc_state *pipe_config,
const char *context)
{
DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
@@ -10087,14 +10087,14 @@ static bool check_digital_port_conflicts(struct drm_device *dev)
return true;
}
-static struct intel_crtc_config *
+static struct intel_crtc_state *
intel_modeset_pipe_config(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_display_mode *mode)
{
struct drm_device *dev = crtc->dev;
struct intel_encoder *encoder;
- struct intel_crtc_config *pipe_config;
+ struct intel_crtc_state *pipe_config;
int plane_bpp, ret = -EINVAL;
bool retry = true;
@@ -10388,8 +10388,8 @@ static bool intel_fuzzy_clock_check(int clock1, int clock2)
static bool
intel_pipe_config_compare(struct drm_device *dev,
- struct intel_crtc_config *current_config,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *current_config,
+ struct intel_crtc_state *pipe_config)
{
#define PIPE_CONF_CHECK_X(name) \
if (current_config->name != pipe_config->name) { \
@@ -10713,7 +10713,7 @@ check_crtc_state(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
- struct intel_crtc_config pipe_config;
+ struct intel_crtc_state pipe_config;
for_each_intel_crtc(dev, crtc) {
bool enabled = false;
@@ -10832,7 +10832,7 @@ intel_modeset_check_state(struct drm_device *dev)
check_shared_dpll_state(dev);
}
-void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
+void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
int dotclock)
{
/*
@@ -10882,7 +10882,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
crtc->scanline_offset = 1;
}
-static struct intel_crtc_config *
+static struct intel_crtc_state *
intel_modeset_compute_config(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_framebuffer *fb,
@@ -10890,7 +10890,7 @@ intel_modeset_compute_config(struct drm_crtc *crtc,
unsigned *prepare_pipes,
unsigned *disable_pipes)
{
- struct intel_crtc_config *pipe_config = NULL;
+ struct intel_crtc_state *pipe_config = NULL;
intel_modeset_affected_pipes(crtc, modeset_pipes,
prepare_pipes, disable_pipes);
@@ -10918,7 +10918,7 @@ out:
static int __intel_set_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode,
int x, int y, struct drm_framebuffer *fb,
- struct intel_crtc_config *pipe_config,
+ struct intel_crtc_state *pipe_config,
unsigned modeset_pipes,
unsigned prepare_pipes,
unsigned disable_pipes)
@@ -11040,7 +11040,7 @@ done:
static int intel_set_mode_pipes(struct drm_crtc *crtc,
struct drm_display_mode *mode,
int x, int y, struct drm_framebuffer *fb,
- struct intel_crtc_config *pipe_config,
+ struct intel_crtc_state *pipe_config,
unsigned modeset_pipes,
unsigned prepare_pipes,
unsigned disable_pipes)
@@ -11060,7 +11060,7 @@ static int intel_set_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode,
int x, int y, struct drm_framebuffer *fb)
{
- struct intel_crtc_config *pipe_config;
+ struct intel_crtc_state *pipe_config;
unsigned modeset_pipes, prepare_pipes, disable_pipes;
pipe_config = intel_modeset_compute_config(crtc, mode, fb,
@@ -11404,7 +11404,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
struct drm_device *dev;
struct drm_mode_set save_set;
struct intel_set_config *config;
- struct intel_crtc_config *pipe_config;
+ struct intel_crtc_state *pipe_config;
unsigned modeset_pipes, prepare_pipes, disable_pipes;
int ret;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3fc3296..8852bd9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1074,7 +1074,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
}
static void
-skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw)
+skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
{
u32 ctrl1;
@@ -1101,7 +1101,7 @@ skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw)
}
static void
-hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
+hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
{
switch (link_bw) {
case DP_LINK_BW_1_62:
@@ -1118,7 +1118,7 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
static void
intel_dp_set_clock(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config, int link_bw)
+ struct intel_crtc_state *pipe_config, int link_bw)
{
struct drm_device *dev = encoder->base.dev;
const struct dp_link_dpll *divisor = NULL;
@@ -1151,7 +1151,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
bool
intel_dp_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2013,7 +2013,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
}
static void intel_dp_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
u32 tmp, flags = 0;
@@ -4750,7 +4750,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *encoder;
struct intel_dp *intel_dp = NULL;
- struct intel_crtc_config *config = NULL;
+ struct intel_crtc_state *config = NULL;
struct intel_crtc *intel_crtc = NULL;
struct intel_connector *intel_connector = dev_priv->drrs.connector;
u32 reg, val;
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index bfe3595..d696c0c 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -30,7 +30,7 @@
#include <drm/drm_edid.h>
static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
@@ -216,7 +216,7 @@ static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
}
static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 61a88fa..e0fe47b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -143,7 +143,7 @@ struct intel_encoder {
bool connectors_active;
void (*hot_plug)(struct intel_encoder *);
bool (*compute_config)(struct intel_encoder *,
- struct intel_crtc_config *);
+ struct intel_crtc_state *);
void (*pre_pll_enable)(struct intel_encoder *);
void (*pre_enable)(struct intel_encoder *);
void (*enable)(struct intel_encoder *);
@@ -159,7 +159,7 @@ struct intel_encoder {
* pre-filled the pipe config. Note that intel_encoder->base.crtc must
* be set correctly before calling this function. */
void (*get_config)(struct intel_encoder *,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
/*
* Called during system suspend after all pending requests for the
* encoder are flushed (for example for DP AUX transactions) and
@@ -259,7 +259,7 @@ struct intel_plane_config {
u32 base;
};
-struct intel_crtc_config {
+struct intel_crtc_state {
/**
* quirks - bitfield with hw state readout quirks
*
@@ -447,8 +447,8 @@ struct intel_crtc {
uint32_t cursor_base;
struct intel_plane_config plane_config;
- struct intel_crtc_config config;
- struct intel_crtc_config *new_config;
+ struct intel_crtc_state config;
+ struct intel_crtc_state *new_config;
bool new_enabled;
/* reset counter value when the last flip was submitted */
@@ -832,11 +832,11 @@ void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
void intel_ddi_fdi_disable(struct drm_crtc *crtc);
void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
void intel_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
/* intel_frontbuffer.c */
@@ -967,11 +967,11 @@ void intel_finish_reset(struct drm_device *dev);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
void intel_dp_set_m_n(struct intel_crtc *crtc);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
void
-ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
+ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
int dotclock);
bool intel_crtc_active(struct drm_crtc *crtc);
void hsw_enable_ips(struct intel_crtc *crtc);
@@ -979,7 +979,7 @@ void hsw_disable_ips(struct intel_crtc *crtc);
enum intel_display_power_domain
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
int intel_format_to_fourcc(int format);
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
@@ -996,7 +996,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder);
void intel_dp_check_link_status(struct intel_dp *intel_dp);
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
bool intel_dp_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
bool intel_dp_is_edp(struct drm_device *dev, enum port port);
bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
bool long_hpd);
@@ -1069,7 +1069,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
struct intel_connector *intel_connector);
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config);
+ struct intel_crtc_state *pipe_config);
/* intel_lvds.c */
@@ -1104,10 +1104,10 @@ void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
void intel_pch_panel_fitting(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config,
+ struct intel_crtc_state *pipe_config,
int fitting_mode);
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config,
+ struct intel_crtc_state *pipe_config,
int fitting_mode);
void intel_panel_set_backlight_acpi(struct intel_connector *connector,
u32 level, u32 max);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8f8b952..adfcc3f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -78,7 +78,7 @@ static void intel_dsi_hot_plug(struct intel_encoder *encoder)
}
static bool intel_dsi_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *config)
+ struct intel_crtc_state *config)
{
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
@@ -420,7 +420,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
}
static void intel_dsi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
u32 pclk;
DRM_DEBUG_KMS("\n");
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index e40e3df..34bee56 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -144,7 +144,7 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
}
static void intel_dvo_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
@@ -200,7 +200,7 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
{
struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
struct drm_crtc *crtc;
- struct intel_crtc_config *config;
+ struct intel_crtc_state *config;
/* dvo supports only 2 dpms states. */
if (mode != DRM_MODE_DPMS_ON)
@@ -261,7 +261,7 @@ intel_dvo_mode_valid(struct drm_connector *connector,
}
static bool intel_dvo_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 3abc200..657452b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -759,7 +759,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
}
static void intel_hdmi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
struct drm_device *dev = encoder->base.dev;
@@ -975,7 +975,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
}
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
struct drm_device *dev = encoder->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 14654d6..f8e2f13 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -93,7 +93,7 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
}
static void intel_lvds_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -277,7 +277,7 @@ intel_lvds_mode_valid(struct drm_connector *connector,
}
static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = intel_encoder->base.dev;
struct intel_lvds_encoder *lvds_encoder =
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 4d63839..c3c5ed4 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -98,7 +98,7 @@ intel_find_panel_downclock(struct drm_device *dev,
/* adjusted_mode has been preset to be the panel's fixed mode */
void
intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
- struct intel_crtc_config *pipe_config,
+ struct intel_crtc_state *pipe_config,
int fitting_mode)
{
struct drm_display_mode *adjusted_mode;
@@ -223,7 +223,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
return (FACTOR * ratio + FACTOR/2) / FACTOR;
}
-static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
+static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
u32 *pfit_control)
{
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
@@ -243,7 +243,7 @@ static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
*pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
}
-static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
+static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
u32 *pfit_control, u32 *pfit_pgm_ratios,
u32 *border)
{
@@ -301,7 +301,7 @@ static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
}
void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
- struct intel_crtc_config *pipe_config,
+ struct intel_crtc_state *pipe_config,
int fitting_mode)
{
struct drm_device *dev = intel_crtc->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 78911e2..c27e800 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3174,7 +3174,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
}
-static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_config *config)
+static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
{
/* TODO: Take into account the scalers once we support them */
return config->adjusted_mode.crtc_clock;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 6d7a277..7e1eb65 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1085,7 +1085,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
return true;
}
-static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
+static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
{
unsigned dotclock = pipe_config->port_clock;
struct dpll *clock = &pipe_config->dpll;
@@ -1112,7 +1112,7 @@ static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
}
static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
@@ -1338,7 +1338,7 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
}
static void intel_sdvo_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 6f5f59b..1a57236 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -908,14 +908,14 @@ intel_tv_mode_valid(struct drm_connector *connector,
static void
intel_tv_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static bool
intel_tv_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
{
struct intel_tv *intel_tv = enc_to_tv(encoder);
const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 2/8] drm/i915: Embedded struct drm_crtc_state in intel_crtc_state
2014-12-11 12:38 [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync Ander Conselvan de Oliveira
2014-12-11 12:38 ` [PATCH 1/8] drm/i915: Rename struct intel_crtc_config to intel_crtc_state Ander Conselvan de Oliveira
@ 2014-12-11 12:38 ` Ander Conselvan de Oliveira
2014-12-11 12:38 ` [PATCH 3/8] drm/i915: Pass new_config down do crtc_compute_clock Ander Conselvan de Oliveira
` (5 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-11 12:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, shuang.he
And get rid of the duplicate mode structures. The bulk of the patch
was generated with the following semantic patch.
@@ struct intel_crtc_state *state; @@
-state->adjusted_mode
+state->base.adjusted_mode
@@ struct intel_crtc_state *state; @@
-state->requested_mode
+state->base.mode
@@ struct intel_crtc_state state; @@
-state.adjusted_mode
+state.base.adjusted_mode
@@ struct intel_crtc_state state; @@
-state.requested_mode
+state.base.mode
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/intel_audio.c | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 10 +--
drivers/gpu/drm/i915/intel_ddi.c | 18 ++---
drivers/gpu/drm/i915/intel_display.c | 147 ++++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_dp.c | 8 +-
drivers/gpu/drm/i915/intel_dp_mst.c | 4 +-
drivers/gpu/drm/i915/intel_drv.h | 12 +--
drivers/gpu/drm/i915/intel_dsi.c | 8 +-
drivers/gpu/drm/i915/intel_dvo.c | 12 +--
drivers/gpu/drm/i915/intel_fbdev.c | 8 +-
drivers/gpu/drm/i915/intel_hdmi.c | 16 ++--
drivers/gpu/drm/i915/intel_lvds.c | 8 +-
drivers/gpu/drm/i915/intel_panel.c | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 30 +++----
drivers/gpu/drm/i915/intel_psr.c | 2 +-
drivers/gpu/drm/i915/intel_sdvo.c | 12 +--
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
drivers/gpu/drm/i915/intel_tv.c | 6 +-
19 files changed, 157 insertions(+), 164 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 08a5a4b..11e209e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -567,7 +567,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
struct intel_crtc *intel_crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
const struct drm_display_mode *mode =
- &intel_crtc->config.adjusted_mode;
+ &intel_crtc->config.base.adjusted_mode;
htotal = mode->crtc_htotal;
hsync_start = mode->crtc_hsync_start;
@@ -638,7 +638,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+ const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
enum pipe pipe = crtc->pipe;
int position, vtotal;
@@ -665,7 +665,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
+ const struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
bool in_vbl = true;
@@ -823,7 +823,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
vblank_time, flags,
crtc,
- &to_intel_crtc(crtc)->config.adjusted_mode);
+ &to_intel_crtc(crtc)->config.base.adjusted_mode);
}
static bool intel_hpd_irq_event(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 2c7ed5c..fe8c496 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -397,7 +397,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
{
struct drm_encoder *encoder = &intel_encoder->base;
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
- struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+ struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
struct drm_connector *connector;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 675b85a..e4f6d49 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -115,14 +115,14 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
struct drm_device *dev = encoder->base.dev;
int dotclock;
- pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
+ pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
dotclock = pipe_config->port_clock;
if (HAS_PCH_SPLIT(dev))
ironlake_check_encoder_dotclock(pipe_config, dotclock);
- pipe_config->adjusted_mode.crtc_clock = dotclock;
+ pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
static void hsw_crt_get_config(struct intel_encoder *encoder,
@@ -130,11 +130,11 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
{
intel_ddi_get_config(encoder, pipe_config);
- pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
+ pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
DRM_MODE_FLAG_NHSYNC |
DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_NVSYNC);
- pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
+ pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
}
static void hsw_crt_pre_enable(struct intel_encoder *encoder)
@@ -157,7 +157,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crt *crt = intel_encoder_to_crt(encoder);
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
u32 adpa;
if (INTEL_INFO(dev)->gen >= 5)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9d69b61..79c9776 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -768,11 +768,11 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
pipe_config->port_clock = link_clock;
if (pipe_config->has_dp_encoder)
- pipe_config->adjusted_mode.crtc_clock =
+ pipe_config->base.adjusted_mode.crtc_clock =
intel_dotclock_calculate(pipe_config->port_clock,
&pipe_config->dp_m_n);
else
- pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+ pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
@@ -820,15 +820,15 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
pipe_config->port_clock = link_clock * 2;
if (pipe_config->has_pch_encoder)
- pipe_config->adjusted_mode.crtc_clock =
+ pipe_config->base.adjusted_mode.crtc_clock =
intel_dotclock_calculate(pipe_config->port_clock,
&pipe_config->fdi_m_n);
else if (pipe_config->has_dp_encoder)
- pipe_config->adjusted_mode.crtc_clock =
+ pipe_config->base.adjusted_mode.crtc_clock =
intel_dotclock_calculate(pipe_config->port_clock,
&pipe_config->dp_m_n);
else
- pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+ pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
void intel_ddi_clock_get(struct intel_encoder *encoder,
@@ -1256,9 +1256,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
BUG();
}
- if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
+ if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
temp |= TRANS_DDI_PVSYNC;
- if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
+ if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
temp |= TRANS_DDI_PHSYNC;
if (cpu_transcoder == TRANSCODER_EDP) {
@@ -1528,7 +1528,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
intel_hdmi->set_infoframes(encoder,
crtc->config.has_hdmi_sink,
- &crtc->config.adjusted_mode);
+ &crtc->config.base.adjusted_mode);
}
}
@@ -2041,7 +2041,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
else
flags |= DRM_MODE_FLAG_NVSYNC;
- pipe_config->adjusted_mode.flags |= flags;
+ pipe_config->base.adjusted_mode.flags |= flags;
switch (temp & TRANS_DDI_BPC_MASK) {
case TRANS_DDI_BPC_6:
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0b1a0af..f836f67 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -895,7 +895,7 @@ bool intel_crtc_active(struct drm_crtc *crtc)
* properly reconstruct framebuffers.
*/
return intel_crtc->active && crtc->primary->fb &&
- intel_crtc->config.adjusted_mode.crtc_clock;
+ intel_crtc->config.base.adjusted_mode.crtc_clock;
}
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -2938,7 +2938,7 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
* then update the pipesrc and pfit state, even on the flip path.
*/
- adjusted_mode = &crtc->config.adjusted_mode;
+ adjusted_mode = &crtc->config.base.adjusted_mode;
I915_WRITE(PIPESRC(crtc->pipe),
((adjusted_mode->crtc_hdisplay - 1) << 16) |
@@ -3574,7 +3574,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
+ int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
u32 divsel, phaseinc, auxdiv, phasedir = 0;
u32 temp;
@@ -4905,7 +4905,7 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
for_each_intel_crtc(dev, intel_crtc) {
if (intel_crtc->new_enabled)
max_pixclk = max(max_pixclk,
- intel_crtc->new_config->adjusted_mode.crtc_clock);
+ intel_crtc->new_config->base.adjusted_mode.crtc_clock);
}
return max_pixclk;
@@ -5426,7 +5426,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = intel_crtc->base.dev;
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
int lane, link_bw, fdi_dotclock;
bool setup_ok, needs_recompute = false;
@@ -5481,7 +5481,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
/* FIXME should check pixel clock limits on all platforms */
if (INTEL_INFO(dev)->gen < 4) {
@@ -6203,7 +6203,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
enum pipe pipe = intel_crtc->pipe;
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.adjusted_mode;
+ &intel_crtc->config.base.adjusted_mode;
uint32_t crtc_vtotal, crtc_vblank_end;
int vsyncshift = 0;
@@ -6274,56 +6274,56 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
uint32_t tmp;
tmp = I915_READ(HTOTAL(cpu_transcoder));
- pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
- pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
tmp = I915_READ(HBLANK(cpu_transcoder));
- pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
- pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
tmp = I915_READ(HSYNC(cpu_transcoder));
- pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
- pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
tmp = I915_READ(VTOTAL(cpu_transcoder));
- pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
- pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
tmp = I915_READ(VBLANK(cpu_transcoder));
- pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
- pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
tmp = I915_READ(VSYNC(cpu_transcoder));
- pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
- pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
+ pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
- pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
- pipe_config->adjusted_mode.crtc_vtotal += 1;
- pipe_config->adjusted_mode.crtc_vblank_end += 1;
+ pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
+ pipe_config->base.adjusted_mode.crtc_vtotal += 1;
+ pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
}
tmp = I915_READ(PIPESRC(crtc->pipe));
pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
- pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
- pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
+ pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
+ pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
}
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config)
{
- mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
- mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
- mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
- mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
+ mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
+ mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
+ mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
+ mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
- mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
- mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
- mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
- mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
+ mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
+ mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
+ mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
+ mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
- mode->flags = pipe_config->adjusted_mode.flags;
+ mode->flags = pipe_config->base.adjusted_mode.flags;
- mode->clock = pipe_config->adjusted_mode.crtc_clock;
- mode->flags |= pipe_config->adjusted_mode.flags;
+ mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
+ mode->flags |= pipe_config->base.adjusted_mode.flags;
}
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
@@ -6373,7 +6373,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
}
}
- if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
if (INTEL_INFO(dev)->gen < 4 ||
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
@@ -7130,7 +7130,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
if (intel_crtc->config.dither)
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
- if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
val |= PIPECONF_INTERLACED_ILK;
else
val |= PIPECONF_PROGRESSIVE;
@@ -7220,7 +7220,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
if (IS_HASWELL(dev) && intel_crtc->config.dither)
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
- if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
val |= PIPECONF_INTERLACED_ILK;
else
val |= PIPECONF_PROGRESSIVE;
@@ -8786,7 +8786,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
* agree once we know their relationship in the encoder's
* get_config() function.
*/
- pipe_config->adjusted_mode.crtc_clock =
+ pipe_config->base.adjusted_mode.crtc_clock =
intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
&pipe_config->fdi_m_n);
}
@@ -9985,10 +9985,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
pipe_config->has_infoframe);
DRM_DEBUG_KMS("requested mode:\n");
- drm_mode_debug_printmodeline(&pipe_config->requested_mode);
+ drm_mode_debug_printmodeline(&pipe_config->base.mode);
DRM_DEBUG_KMS("adjusted mode:\n");
- drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
- intel_dump_crtc_timings(&pipe_config->adjusted_mode);
+ drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
+ intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
DRM_DEBUG_KMS("pipe src size: %dx%d\n",
pipe_config->pipe_src_w, pipe_config->pipe_src_h);
@@ -10112,8 +10112,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
if (!pipe_config)
return ERR_PTR(-ENOMEM);
- drm_mode_copy(&pipe_config->adjusted_mode, mode);
- drm_mode_copy(&pipe_config->requested_mode, mode);
+ drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
+ drm_mode_copy(&pipe_config->base.mode, mode);
pipe_config->cpu_transcoder =
(enum transcoder) to_intel_crtc(crtc)->pipe;
@@ -10124,13 +10124,13 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
* positive or negative polarity is requested, treat this as meaning
* negative polarity.
*/
- if (!(pipe_config->adjusted_mode.flags &
+ if (!(pipe_config->base.adjusted_mode.flags &
(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
- pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
+ pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
- if (!(pipe_config->adjusted_mode.flags &
+ if (!(pipe_config->base.adjusted_mode.flags &
(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
- pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
+ pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
/* Compute a starting value for pipe_config->pipe_bpp taking the source
* plane pixel format and any sink constraints into account. Returns the
@@ -10149,7 +10149,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
* computation to clearly distinguish it from the adjusted mode, which
* can be changed by the connectors in the below retry loop.
*/
- drm_crtc_get_hv_timing(&pipe_config->requested_mode,
+ drm_crtc_get_hv_timing(&pipe_config->base.mode,
&pipe_config->pipe_src_w,
&pipe_config->pipe_src_h);
@@ -10159,7 +10159,8 @@ encoder_retry:
pipe_config->pixel_multiplier = 1;
/* Fill in default crtc timings, allow encoders to overwrite them. */
- drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
+ drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
+ CRTC_STEREO_DOUBLE);
/* Pass our mode to the connectors and the CRTC to give them a chance to
* adjust it according to limitations or connector properties, and also
@@ -10179,7 +10180,7 @@ encoder_retry:
/* Set default port clock if not overwritten by the encoder. Needs to be
* done afterwards in case the encoder adjusts the mode. */
if (!pipe_config->port_clock)
- pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
+ pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
* pipe_config->pixel_multiplier;
ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
@@ -10480,19 +10481,19 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
}
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(has_hdmi_sink);
@@ -10503,17 +10504,17 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I(has_audio);
- PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
DRM_MODE_FLAG_INTERLACE);
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
DRM_MODE_FLAG_NVSYNC);
}
@@ -10563,7 +10564,7 @@ intel_pipe_config_compare(struct drm_device *dev,
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
#undef PIPE_CONF_CHECK_X
@@ -10839,9 +10840,9 @@ void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
* FDI already provided one idea for the dotclock.
* Yell if the encoder disagrees.
*/
- WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
+ WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
"FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
- pipe_config->adjusted_mode.crtc_clock, dotclock);
+ pipe_config->base.adjusted_mode.crtc_clock, dotclock);
}
static void update_scanline_offset(struct intel_crtc *crtc)
@@ -10867,7 +10868,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
* one to the value.
*/
if (IS_GEN2(dev)) {
- const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+ const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
int vtotal;
vtotal = mode->crtc_vtotal;
@@ -10996,7 +10997,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
* timestamping. They are derived from true hwmode.
*/
drm_calc_timestamping_constants(crtc,
- &pipe_config->adjusted_mode);
+ &pipe_config->base.adjusted_mode);
}
/* Only after disabling all output pipelines that will be changed can we
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8852bd9..67cdbe8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1155,7 +1155,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = dp_to_dig_port(intel_dp)->port;
struct intel_crtc *intel_crtc = encoder->new_crtc;
@@ -1324,7 +1324,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = dp_to_dig_port(intel_dp)->port;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
/*
* There are four kinds of DP registers:
@@ -2050,7 +2050,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
flags |= DRM_MODE_FLAG_NVSYNC;
}
- pipe_config->adjusted_mode.flags |= flags;
+ pipe_config->base.adjusted_mode.flags |= flags;
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
tmp & DP_COLOR_RANGE_16_235)
@@ -2073,7 +2073,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
ironlake_check_encoder_dotclock(pipe_config, dotclock);
- pipe_config->adjusted_mode.crtc_clock = dotclock;
+ pipe_config->base.adjusted_mode.crtc_clock = dotclock;
if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index d696c0c..257aca1 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct drm_device *dev = encoder->base.dev;
int bpp;
int lane_count, slots;
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
struct intel_connector *found = NULL, *intel_connector;
int mst_pbn;
@@ -254,7 +254,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
default:
break;
}
- pipe_config->adjusted_mode.flags |= flags;
+ pipe_config->base.adjusted_mode.flags |= flags;
intel_dp_get_m_n(crtc, pipe_config);
intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e0fe47b..c55c454 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -260,6 +260,8 @@ struct intel_plane_config {
};
struct intel_crtc_state {
+ struct drm_crtc_state base;
+
/**
* quirks - bitfield with hw state readout quirks
*
@@ -272,16 +274,6 @@ struct intel_crtc_state {
#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
unsigned long quirks;
- /* User requested mode, only valid as a starting point to
- * compute adjusted_mode, except in the case of (S)DVO where
- * it's also for the output timings of the (S)DVO chip.
- * adjusted_mode will then correspond to the S(DVO) chip's
- * preferred input timings. */
- struct drm_display_mode requested_mode;
- /* Actual pipe timings ie. what we program into the pipe timing
- * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
- struct drm_display_mode adjusted_mode;
-
/* Pipe source size (ie. panel fitter input size)
* All planes will be positioned inside this space,
* and get clipped at the edges. */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index adfcc3f..25291e9 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -84,8 +84,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
- struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
- struct drm_display_mode *mode = &config->requested_mode;
+ struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
+ struct drm_display_mode *mode = &config->base.mode;
DRM_DEBUG_KMS("\n");
@@ -435,7 +435,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
if (!pclk)
return;
- pipe_config->adjusted_mode.crtc_clock = pclk;
+ pipe_config->base.adjusted_mode.crtc_clock = pclk;
pipe_config->port_clock = pclk;
}
@@ -549,7 +549,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.adjusted_mode;
+ &intel_crtc->config.base.adjusted_mode;
enum port port;
unsigned int bpp = intel_crtc->config.pipe_bpp;
u32 val, tmp;
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 34bee56..108f058 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -160,9 +160,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
else
flags |= DRM_MODE_FLAG_NVSYNC;
- pipe_config->adjusted_mode.flags |= flags;
+ pipe_config->base.adjusted_mode.flags |= flags;
- pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+ pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static void intel_disable_dvo(struct intel_encoder *encoder)
@@ -186,8 +186,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
u32 temp = I915_READ(dvo_reg);
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
- &crtc->config.requested_mode,
- &crtc->config.adjusted_mode);
+ &crtc->config.base.mode,
+ &crtc->config.base.adjusted_mode);
I915_WRITE(dvo_reg, temp | DVO_ENABLE);
I915_READ(dvo_reg);
@@ -264,7 +264,7 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
/* If we have timings from the BIOS for the panel, put them in
* to the adjusted mode. The CRTC will be set up for this mode,
@@ -295,7 +295,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
int pipe = crtc->pipe;
u32 dvo_val;
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index f2183b5..1a9a727 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -563,7 +563,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
* pipe. Note we need to use the selected fb's pitch and bpp
* rather than the current pipe's, since they differ.
*/
- cur_size = intel_crtc->config.adjusted_mode.crtc_hdisplay;
+ cur_size = intel_crtc->config.base.adjusted_mode.crtc_hdisplay;
cur_size = cur_size * fb->base.bits_per_pixel / 8;
if (fb->base.pitches[0] < cur_size) {
DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n",
@@ -574,13 +574,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
break;
}
- cur_size = intel_crtc->config.adjusted_mode.crtc_vdisplay;
+ cur_size = intel_crtc->config.base.adjusted_mode.crtc_vdisplay;
cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1);
cur_size *= fb->base.pitches[0];
DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
pipe_name(intel_crtc->pipe),
- intel_crtc->config.adjusted_mode.crtc_hdisplay,
- intel_crtc->config.adjusted_mode.crtc_vdisplay,
+ intel_crtc->config.base.adjusted_mode.crtc_hdisplay,
+ intel_crtc->config.base.adjusted_mode.crtc_vdisplay,
fb->base.bits_per_pixel,
cur_size);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 657452b..02ff3e2 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -700,7 +700,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
- struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
u32 hdmi_val;
hdmi_val = SDVO_ENCODING_HDMI;
@@ -792,7 +792,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
tmp & HDMI_COLOR_RANGE_16_235)
pipe_config->limited_color_range = true;
- pipe_config->adjusted_mode.flags |= flags;
+ pipe_config->base.adjusted_mode.flags |= flags;
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
dotclock = pipe_config->port_clock * 2 / 3;
@@ -802,7 +802,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev_priv->dev))
ironlake_check_encoder_dotclock(pipe_config, dotclock);
- pipe_config->adjusted_mode.crtc_clock = dotclock;
+ pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
static void intel_enable_hdmi(struct intel_encoder *encoder)
@@ -979,8 +979,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
struct drm_device *dev = encoder->base.dev;
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
- int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
int desired_bpp;
@@ -1252,7 +1252,7 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.adjusted_mode;
+ &intel_crtc->config.base.adjusted_mode;
intel_hdmi_prepare(encoder);
@@ -1270,7 +1270,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.adjusted_mode;
+ &intel_crtc->config.base.adjusted_mode;
enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe;
u32 val;
@@ -1467,7 +1467,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.adjusted_mode;
+ &intel_crtc->config.base.adjusted_mode;
enum dpio_channel ch = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe;
int data, i;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index f8e2f13..9d174cf 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -115,7 +115,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
else
flags |= DRM_MODE_FLAG_PVSYNC;
- pipe_config->adjusted_mode.flags |= flags;
+ pipe_config->base.adjusted_mode.flags |= flags;
/* gen2/3 store dither state in pfit control, needs to match */
if (INTEL_INFO(dev)->gen < 4) {
@@ -129,7 +129,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev_priv->dev))
ironlake_check_encoder_dotclock(pipe_config, dotclock);
- pipe_config->adjusted_mode.crtc_clock = dotclock;
+ pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
static void intel_pre_enable_lvds(struct intel_encoder *encoder)
@@ -139,7 +139,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
const struct drm_display_mode *adjusted_mode =
- &crtc->config.adjusted_mode;
+ &crtc->config.base.adjusted_mode;
int pipe = crtc->pipe;
u32 temp;
@@ -284,7 +284,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
to_lvds_encoder(&intel_encoder->base);
struct intel_connector *intel_connector =
&lvds_encoder->attached_connector->base;
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
unsigned int lvds_bpp;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c3c5ed4..d7be68a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -104,7 +104,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
struct drm_display_mode *adjusted_mode;
int x, y, width, height;
- adjusted_mode = &pipe_config->adjusted_mode;
+ adjusted_mode = &pipe_config->base.adjusted_mode;
x = y = width = height = 0;
@@ -226,7 +226,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
u32 *pfit_control)
{
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
u32 scaled_width = adjusted_mode->hdisplay *
pipe_config->pipe_src_h;
u32 scaled_height = pipe_config->pipe_src_w *
@@ -247,7 +247,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
u32 *pfit_control, u32 *pfit_pgm_ratios,
u32 *border)
{
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
u32 scaled_width = adjusted_mode->hdisplay *
pipe_config->pipe_src_h;
u32 scaled_height = pipe_config->pipe_src_w *
@@ -308,7 +308,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
struct drm_display_mode *adjusted_mode;
- adjusted_mode = &pipe_config->adjusted_mode;
+ adjusted_mode = &pipe_config->base.adjusted_mode;
/* Native modes don't need fitting */
if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c27e800..47b23b7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -574,7 +574,7 @@ void intel_update_fbc(struct drm_device *dev)
intel_crtc = to_intel_crtc(crtc);
fb = crtc->primary->fb;
obj = intel_fb_obj(fb);
- adjusted_mode = &intel_crtc->config.adjusted_mode;
+ adjusted_mode = &intel_crtc->config.base.adjusted_mode;
if (i915.enable_fbc < 0) {
if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
@@ -1157,7 +1157,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
int clock;
- adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
clock = adjusted_mode->crtc_clock;
/* Display SR */
@@ -1226,7 +1226,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
return false;
}
- adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
@@ -1313,7 +1313,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
}
crtc = intel_get_crtc_for_plane(dev, plane);
- adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
@@ -1347,7 +1347,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
int entries;
- int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
+ int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
if (WARN(clock == 0, "Pixel clock is zero!\n"))
return false;
@@ -1677,7 +1677,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
/* self-refresh has much higher latency */
static const int sr_latency_ns = 12000;
const struct drm_display_mode *adjusted_mode =
- &to_intel_crtc(crtc)->config.adjusted_mode;
+ &to_intel_crtc(crtc)->config.base.adjusted_mode;
int clock = adjusted_mode->crtc_clock;
int htotal = adjusted_mode->crtc_htotal;
int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
@@ -1762,7 +1762,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (IS_GEN2(dev))
cpp = 4;
- adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
@@ -1784,7 +1784,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (IS_GEN2(dev))
cpp = 4;
- adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
@@ -1823,7 +1823,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
const struct drm_display_mode *adjusted_mode =
- &to_intel_crtc(enabled)->config.adjusted_mode;
+ &to_intel_crtc(enabled)->config.base.adjusted_mode;
int clock = adjusted_mode->crtc_clock;
int htotal = adjusted_mode->crtc_htotal;
int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
@@ -1879,7 +1879,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
if (crtc == NULL)
return;
- adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
&i845_wm_info,
dev_priv->display.get_fifo_size(dev, 0),
@@ -1898,7 +1898,7 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pixel_rate;
- pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
+ pixel_rate = intel_crtc->config.base.adjusted_mode.crtc_clock;
/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
* adjust the pixel_rate here. */
@@ -2261,7 +2261,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
+ struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
u32 linetime, ips_linetime;
if (!intel_crtc_active(crtc))
@@ -2521,7 +2521,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
return;
p->active = true;
- p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
+ p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
p->cur.bytes_per_pixel = 4;
@@ -3177,7 +3177,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
{
/* TODO: Take into account the scalers once we support them */
- return config->adjusted_mode.crtc_clock;
+ return config->base.adjusted_mode.crtc_clock;
}
/*
@@ -3265,7 +3265,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
p->active = intel_crtc_active(crtc);
if (p->active) {
- p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
+ p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
/*
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index dd0e6e0..b8713e4 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,7 +280,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
return false;
}
- if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
return false;
}
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 7e1eb65..e4d5da5 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1115,8 +1115,8 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
- struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
- struct drm_display_mode *mode = &pipe_config->requested_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *mode = &pipe_config->base.mode;
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
pipe_config->pipe_bpp = 8*3;
@@ -1181,8 +1181,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
- &crtc->config.adjusted_mode;
- struct drm_display_mode *mode = &crtc->config.requested_mode;
+ &crtc->config.base.adjusted_mode;
+ struct drm_display_mode *mode = &crtc->config.base.mode;
struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
u32 sdvox;
struct intel_sdvo_in_out_map in_out;
@@ -1370,7 +1370,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
flags |= DRM_MODE_FLAG_NVSYNC;
}
- pipe_config->adjusted_mode.flags |= flags;
+ pipe_config->base.adjusted_mode.flags |= flags;
/*
* pixel multiplier readout is tricky: Only on i915g/gm it is stored in
@@ -1392,7 +1392,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev))
ironlake_check_encoder_dotclock(pipe_config, dotclock);
- pipe_config->adjusted_mode.crtc_clock = dotclock;
+ pipe_config->base.adjusted_mode.crtc_clock = dotclock;
/* Cross check the port pixel multiplier with the sdvo encoder state. */
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index bc5834b..454b25d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -79,7 +79,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
{
struct drm_device *dev = crtc->base.dev;
- const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+ const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
enum pipe pipe = crtc->pipe;
long timeout = msecs_to_jiffies_timeout(1);
int scanline, min, max, vblank_start;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 1a57236..10e7ebd 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -910,7 +910,7 @@ static void
intel_tv_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+ pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static bool
@@ -923,12 +923,12 @@ intel_tv_compute_config(struct intel_encoder *encoder,
if (!tv_mode)
return false;
- pipe_config->adjusted_mode.crtc_clock = tv_mode->clock;
+ pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock;
DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
pipe_config->pipe_bpp = 8*3;
/* TV has it's own notion of sync and other mode flags, so clear them. */
- pipe_config->adjusted_mode.flags = 0;
+ pipe_config->base.adjusted_mode.flags = 0;
/*
* FIXME: We don't check whether the input mode is actually what we want
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 3/8] drm/i915: Pass new_config down do crtc_compute_clock
2014-12-11 12:38 [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync Ander Conselvan de Oliveira
2014-12-11 12:38 ` [PATCH 1/8] drm/i915: Rename struct intel_crtc_config to intel_crtc_state Ander Conselvan de Oliveira
2014-12-11 12:38 ` [PATCH 2/8] drm/i915: Embedded struct drm_crtc_state in intel_crtc_state Ander Conselvan de Oliveira
@ 2014-12-11 12:38 ` Ander Conselvan de Oliveira
2014-12-11 12:38 ` [PATCH 4/8] drm/i915: Use local pipe_config varariable when available Ander Conselvan de Oliveira
` (4 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-11 12:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, shuang.he
This reduces the number of direct users of crtc->new_config. At some
point we'll be able to get rid of that pointer altogether, in favor
of drm core state structs.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/intel_ddi.c | 29 ++++----
drivers/gpu/drm/i915/intel_display.c | 131 +++++++++++++++++++----------------
drivers/gpu/drm/i915/intel_drv.h | 6 +-
4 files changed, 94 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d60d38..c1a9af9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -500,7 +500,8 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *);
void (*get_plane_config)(struct intel_crtc *,
struct intel_plane_config *);
- int (*crtc_compute_clock)(struct intel_crtc *crtc);
+ int (*crtc_compute_clock)(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct drm_crtc *crtc);
void (*crtc_disable)(struct drm_crtc *crtc);
void (*off)(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 79c9776..970ca30 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -904,6 +904,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
static bool
hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
struct intel_encoder *intel_encoder,
int clock)
{
@@ -918,16 +919,16 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
- intel_crtc->new_config->dpll_hw_state.wrpll = val;
+ crtc_state->dpll_hw_state.wrpll = val;
- pll = intel_get_shared_dpll(intel_crtc);
+ pll = intel_get_shared_dpll(intel_crtc, crtc_state);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
pipe_name(intel_crtc->pipe));
return false;
}
- intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
+ crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
}
return true;
@@ -1090,6 +1091,7 @@ found:
static bool
skl_ddi_pll_select(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
struct intel_encoder *intel_encoder,
int clock)
{
@@ -1139,11 +1141,11 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
} else /* eDP */
return true;
- intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
- intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
- intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
+ crtc_state->dpll_hw_state.ctrl1 = ctrl1;
+ crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
+ crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
- pll = intel_get_shared_dpll(intel_crtc);
+ pll = intel_get_shared_dpll(intel_crtc, crtc_state);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
pipe_name(intel_crtc->pipe));
@@ -1151,7 +1153,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
}
/* shared DPLL id 0 is DPLL 1 */
- intel_crtc->new_config->ddi_pll_sel = pll->id + 1;
+ crtc_state->ddi_pll_sel = pll->id + 1;
return true;
}
@@ -1163,17 +1165,20 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
* For private DPLLs, compute_config() should do the selection for us. This
* function should be folded into compute_config() eventually.
*/
-bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
+bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = intel_crtc->base.dev;
struct intel_encoder *intel_encoder =
intel_ddi_get_crtc_new_encoder(intel_crtc);
- int clock = intel_crtc->new_config->port_clock;
+ int clock = crtc_state->port_clock;
if (IS_SKYLAKE(dev))
- return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
+ return skl_ddi_pll_select(intel_crtc, crtc_state,
+ intel_encoder, clock);
else
- return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
+ return hsw_ddi_pll_select(intel_crtc, crtc_state,
+ intel_encoder, clock);
}
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f836f67..3bceacb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3858,7 +3858,8 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
crtc->config.shared_dpll = DPLL_ID_PRIVATE;
}
-struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
+struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
struct intel_shared_dpll *pll;
@@ -3884,7 +3885,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
if (pll->new_config->crtc_mask == 0)
continue;
- if (memcmp(&crtc->new_config->dpll_hw_state,
+ if (memcmp(&crtc_state->dpll_hw_state,
&pll->new_config->hw_state,
sizeof(pll->new_config->hw_state)) == 0) {
DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
@@ -3909,9 +3910,9 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
found:
if (pll->new_config->crtc_mask == 0)
- pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
+ pll->new_config->hw_state = crtc_state->dpll_hw_state;
- crtc->new_config->shared_dpll = i;
+ crtc_state->shared_dpll = i;
DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
pipe_name(crtc->pipe));
@@ -5726,30 +5727,31 @@ static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
}
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
intel_clock_t *reduced_clock)
{
struct drm_device *dev = crtc->base.dev;
u32 fp, fp2 = 0;
if (IS_PINEVIEW(dev)) {
- fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
+ fp = pnv_dpll_compute_fp(&crtc_state->dpll);
if (reduced_clock)
fp2 = pnv_dpll_compute_fp(reduced_clock);
} else {
- fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
+ fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
if (reduced_clock)
fp2 = i9xx_dpll_compute_fp(reduced_clock);
}
- crtc->new_config->dpll_hw_state.fp0 = fp;
+ crtc_state->dpll_hw_state.fp0 = fp;
crtc->lowfreq_avail = false;
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
reduced_clock && i915.powersave) {
- crtc->new_config->dpll_hw_state.fp1 = fp2;
+ crtc_state->dpll_hw_state.fp1 = fp2;
crtc->lowfreq_avail = true;
} else {
- crtc->new_config->dpll_hw_state.fp1 = fp;
+ crtc_state->dpll_hw_state.fp1 = fp;
}
}
@@ -6084,6 +6086,7 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
}
static void i9xx_update_pll(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
intel_clock_t *reduced_clock,
int num_connectors)
{
@@ -6091,9 +6094,9 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
u32 dpll;
bool is_sdvo;
- struct dpll *clock = &crtc->new_config->dpll;
+ struct dpll *clock = &crtc_state->dpll;
- i9xx_update_pll_dividers(crtc, reduced_clock);
+ i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
@@ -6106,14 +6109,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
dpll |= DPLLB_MODE_DAC_SERIAL;
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
- dpll |= (crtc->new_config->pixel_multiplier - 1)
+ dpll |= (crtc_state->pixel_multiplier - 1)
<< SDVO_MULTIPLIER_SHIFT_HIRES;
}
if (is_sdvo)
dpll |= DPLL_SDVO_HIGH_SPEED;
- if (crtc->new_config->has_dp_encoder)
+ if (crtc_state->has_dp_encoder)
dpll |= DPLL_SDVO_HIGH_SPEED;
/* compute bitmask from p1 value */
@@ -6141,7 +6144,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
if (INTEL_INFO(dev)->gen >= 4)
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
- if (crtc->new_config->sdvo_tv_clock)
+ if (crtc_state->sdvo_tv_clock)
dpll |= PLL_REF_INPUT_TVCLKINBC;
else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
intel_panel_use_ssc(dev_priv) && num_connectors < 2)
@@ -6150,25 +6153,26 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
dpll |= PLL_REF_INPUT_DREFCLK;
dpll |= DPLL_VCO_ENABLE;
- crtc->new_config->dpll_hw_state.dpll = dpll;
+ crtc_state->dpll_hw_state.dpll = dpll;
if (INTEL_INFO(dev)->gen >= 4) {
- u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
+ u32 dpll_md = (crtc_state->pixel_multiplier - 1)
<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
- crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
+ crtc_state->dpll_hw_state.dpll_md = dpll_md;
}
}
static void i8xx_update_pll(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
intel_clock_t *reduced_clock,
int num_connectors)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 dpll;
- struct dpll *clock = &crtc->new_config->dpll;
+ struct dpll *clock = &crtc_state->dpll;
- i9xx_update_pll_dividers(crtc, reduced_clock);
+ i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
dpll = DPLL_VGA_MODE_DIS;
@@ -6193,7 +6197,7 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
dpll |= PLL_REF_INPUT_DREFCLK;
dpll |= DPLL_VCO_ENABLE;
- crtc->new_config->dpll_hw_state.dpll = dpll;
+ crtc_state->dpll_hw_state.dpll = dpll;
}
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
@@ -6389,7 +6393,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
POSTING_READ(PIPECONF(intel_crtc->pipe));
}
-static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
+static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6421,7 +6426,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
if (is_dsi)
return 0;
- if (!crtc->new_config->clock_set) {
+ if (!crtc_state->clock_set) {
refclk = i9xx_get_refclk(crtc, num_connectors);
/*
@@ -6432,7 +6437,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
*/
limit = intel_limit(crtc, refclk);
ok = dev_priv->display.find_dpll(limit, crtc,
- crtc->new_config->port_clock,
+ crtc_state->port_clock,
refclk, NULL, &clock);
if (!ok) {
DRM_ERROR("Couldn't find PLL settings for mode!\n");
@@ -6453,23 +6458,23 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
&reduced_clock);
}
/* Compat-code for transition, will disappear. */
- crtc->new_config->dpll.n = clock.n;
- crtc->new_config->dpll.m1 = clock.m1;
- crtc->new_config->dpll.m2 = clock.m2;
- crtc->new_config->dpll.p1 = clock.p1;
- crtc->new_config->dpll.p2 = clock.p2;
+ crtc_state->dpll.n = clock.n;
+ crtc_state->dpll.m1 = clock.m1;
+ crtc_state->dpll.m2 = clock.m2;
+ crtc_state->dpll.p1 = clock.p1;
+ crtc_state->dpll.p2 = clock.p2;
}
if (IS_GEN2(dev)) {
- i8xx_update_pll(crtc,
+ i8xx_update_pll(crtc, crtc_state,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
} else if (IS_CHERRYVIEW(dev)) {
- chv_update_pll(crtc, crtc->new_config);
+ chv_update_pll(crtc, crtc_state);
} else if (IS_VALLEYVIEW(dev)) {
- vlv_update_pll(crtc, crtc->new_config);
+ vlv_update_pll(crtc, crtc_state);
} else {
- i9xx_update_pll(crtc,
+ i9xx_update_pll(crtc, crtc_state,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
}
@@ -7260,6 +7265,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
}
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
intel_clock_t *clock,
bool *has_reduced_clock,
intel_clock_t *reduced_clock)
@@ -7282,7 +7288,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
*/
limit = intel_limit(intel_crtc, refclk);
ret = dev_priv->display.find_dpll(limit, intel_crtc,
- intel_crtc->new_config->port_clock,
+ crtc_state->port_clock,
refclk, NULL, clock);
if (!ret)
return false;
@@ -7321,6 +7327,7 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
}
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
u32 *fp,
intel_clock_t *reduced_clock, u32 *fp2)
{
@@ -7358,10 +7365,10 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
dev_priv->vbt.lvds_ssc_freq == 100000) ||
(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
factor = 25;
- } else if (intel_crtc->new_config->sdvo_tv_clock)
+ } else if (crtc_state->sdvo_tv_clock)
factor = 20;
- if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
+ if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
*fp |= FP_CB_TUNE;
if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
@@ -7374,20 +7381,20 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
else
dpll |= DPLLB_MODE_DAC_SERIAL;
- dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
+ dpll |= (crtc_state->pixel_multiplier - 1)
<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
if (is_sdvo)
dpll |= DPLL_SDVO_HIGH_SPEED;
- if (intel_crtc->new_config->has_dp_encoder)
+ if (crtc_state->has_dp_encoder)
dpll |= DPLL_SDVO_HIGH_SPEED;
/* compute bitmask from p1 value */
- dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
/* also FPA1 */
- dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+ dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
- switch (intel_crtc->new_config->dpll.p2) {
+ switch (crtc_state->dpll.p2) {
case 5:
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
break;
@@ -7410,7 +7417,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
return dpll | DPLL_VCO_ENABLE;
}
-static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
+static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = crtc->base.dev;
intel_clock_t clock, reduced_clock;
@@ -7424,39 +7432,39 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
- ok = ironlake_compute_clocks(&crtc->base, &clock,
+ ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
&has_reduced_clock, &reduced_clock);
- if (!ok && !crtc->new_config->clock_set) {
+ if (!ok && !crtc_state->clock_set) {
DRM_ERROR("Couldn't find PLL settings for mode!\n");
return -EINVAL;
}
/* Compat-code for transition, will disappear. */
- if (!crtc->new_config->clock_set) {
- crtc->new_config->dpll.n = clock.n;
- crtc->new_config->dpll.m1 = clock.m1;
- crtc->new_config->dpll.m2 = clock.m2;
- crtc->new_config->dpll.p1 = clock.p1;
- crtc->new_config->dpll.p2 = clock.p2;
+ if (!crtc_state->clock_set) {
+ crtc_state->dpll.n = clock.n;
+ crtc_state->dpll.m1 = clock.m1;
+ crtc_state->dpll.m2 = clock.m2;
+ crtc_state->dpll.p1 = clock.p1;
+ crtc_state->dpll.p2 = clock.p2;
}
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
- if (crtc->new_config->has_pch_encoder) {
- fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
+ if (crtc_state->has_pch_encoder) {
+ fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
if (has_reduced_clock)
fp2 = i9xx_dpll_compute_fp(&reduced_clock);
- dpll = ironlake_compute_dpll(crtc,
+ dpll = ironlake_compute_dpll(crtc, crtc_state,
&fp, &reduced_clock,
has_reduced_clock ? &fp2 : NULL);
- crtc->new_config->dpll_hw_state.dpll = dpll;
- crtc->new_config->dpll_hw_state.fp0 = fp;
+ crtc_state->dpll_hw_state.dpll = dpll;
+ crtc_state->dpll_hw_state.fp0 = fp;
if (has_reduced_clock)
- crtc->new_config->dpll_hw_state.fp1 = fp2;
+ crtc_state->dpll_hw_state.fp1 = fp2;
else
- crtc->new_config->dpll_hw_state.fp1 = fp;
+ crtc_state->dpll_hw_state.fp1 = fp;
- pll = intel_get_shared_dpll(crtc);
+ pll = intel_get_shared_dpll(crtc, crtc_state);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
pipe_name(crtc->pipe));
@@ -7967,9 +7975,10 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
intel_prepare_ddi(dev);
}
-static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
+static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
{
- if (!intel_ddi_pll_select(crtc))
+ if (!intel_ddi_pll_select(crtc, crtc_state))
return -EINVAL;
crtc->lowfreq_avail = false;
@@ -10961,7 +10970,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
goto done;
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
- ret = dev_priv->display.crtc_compute_clock(intel_crtc);
+ struct intel_crtc_state *state = intel_crtc->new_config;
+ ret = dev_priv->display.crtc_compute_clock(intel_crtc,
+ state);
if (ret) {
intel_shared_dpll_abort_config(dev_priv);
goto done;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c55c454..0a84667 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -818,7 +818,8 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder);
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
-bool intel_ddi_pll_select(struct intel_crtc *crtc);
+bool intel_ddi_pll_select(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state);
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
@@ -929,7 +930,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
+struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
+ struct intel_crtc_state *state);
void intel_put_shared_dpll(struct intel_crtc *crtc);
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 4/8] drm/i915: Use local pipe_config varariable when available
2014-12-11 12:38 [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync Ander Conselvan de Oliveira
` (2 preceding siblings ...)
2014-12-11 12:38 ` [PATCH 3/8] drm/i915: Pass new_config down do crtc_compute_clock Ander Conselvan de Oliveira
@ 2014-12-11 12:38 ` Ander Conselvan de Oliveira
2014-12-15 18:37 ` Matt Roper
2014-12-11 12:38 ` [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk() Ander Conselvan de Oliveira
` (3 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-11 12:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, shuang.he
In function that define a local pipe_config variable to point to
crtc->config, replace remaining references to crtc->config with
the local variable. This makes the code more consistent and easier
to change in an automated manner.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3bceacb..da5af23 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4602,7 +4602,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc_state *pipe_config = &crtc->config;
- if (!crtc->config.gmch_pfit.control)
+ if (!pipe_config->gmch_pfit.control)
return;
/*
@@ -5925,7 +5925,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
0x00d0000f);
- if (crtc->config.has_dp_encoder) {
+ if (pipe_config->has_dp_encoder) {
/* Use SSC source */
if (pipe == PIPE_A)
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
@@ -7541,7 +7541,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
- if (crtc->config.has_pch_encoder)
+ if (pipe_config->has_pch_encoder)
intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
else
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 4/8] drm/i915: Use local pipe_config varariable when available
2014-12-11 12:38 ` [PATCH 4/8] drm/i915: Use local pipe_config varariable when available Ander Conselvan de Oliveira
@ 2014-12-15 18:37 ` Matt Roper
2014-12-15 19:21 ` Ville Syrjälä
0 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2014-12-15 18:37 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx, shuang.he
On Thu, Dec 11, 2014 at 02:38:07PM +0200, Ander Conselvan de Oliveira wrote:
> In function that define a local pipe_config variable to point to
> crtc->config, replace remaining references to crtc->config with
> the local variable. This makes the code more consistent and easier
> to change in an automated manner.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3bceacb..da5af23 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4602,7 +4602,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc_state *pipe_config = &crtc->config;
>
> - if (!crtc->config.gmch_pfit.control)
> + if (!pipe_config->gmch_pfit.control)
> return;
>
> /*
> @@ -5925,7 +5925,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
> 0x00d0000f);
>
> - if (crtc->config.has_dp_encoder) {
> + if (pipe_config->has_dp_encoder) {
Does this one change the behavior in some cases? The pipe_config
parameter passed to this function from vlv_force_pll_on() is a hardcoded
pipe_config that is never going to have has_dp_encoder set, regardless
of what the current config is.
> /* Use SSC source */
> if (pipe == PIPE_A)
> vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
> @@ -7541,7 +7541,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> - if (crtc->config.has_pch_encoder)
> + if (pipe_config->has_pch_encoder)
I think this one might also change the semantics? The callchain
check_crtc_state() -> intel_{dp,ddi}_get_config() -> intel_dp_get_m_n()
passes down a fresh pipe_config() that isn't the same structure stored
in crtc->config (although it hopefully has the same values in the end).
Matt
> intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
> else
> intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 4/8] drm/i915: Use local pipe_config varariable when available
2014-12-15 18:37 ` Matt Roper
@ 2014-12-15 19:21 ` Ville Syrjälä
2014-12-16 9:25 ` Daniel Vetter
0 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjälä @ 2014-12-15 19:21 UTC (permalink / raw)
To: Matt Roper; +Cc: Ander Conselvan de Oliveira, intel-gfx, shuang.he
On Mon, Dec 15, 2014 at 10:37:57AM -0800, Matt Roper wrote:
> On Thu, Dec 11, 2014 at 02:38:07PM +0200, Ander Conselvan de Oliveira wrote:
> > In function that define a local pipe_config variable to point to
> > crtc->config, replace remaining references to crtc->config with
> > the local variable. This makes the code more consistent and easier
> > to change in an automated manner.
> >
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3bceacb..da5af23 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4602,7 +4602,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct intel_crtc_state *pipe_config = &crtc->config;
> >
> > - if (!crtc->config.gmch_pfit.control)
> > + if (!pipe_config->gmch_pfit.control)
> > return;
> >
> > /*
> > @@ -5925,7 +5925,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> > vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
> > 0x00d0000f);
> >
> > - if (crtc->config.has_dp_encoder) {
> > + if (pipe_config->has_dp_encoder) {
>
> Does this one change the behavior in some cases? The pipe_config
> parameter passed to this function from vlv_force_pll_on() is a hardcoded
> pipe_config that is never going to have has_dp_encoder set, regardless
> of what the current config is.
The force stuff is only done when the pipe isn't active, so crtc->config
will be stale anyway (well, actually the pipe could be driving DSI but
that shouldn't really matter either).
So using the passed pipe_config leads to a more consistent result. The
value of has_dp_encoder shouldn't actually matter as long as we get
some kind of clock from the DPLL.
>
>
> > /* Use SSC source */
> > if (pipe == PIPE_A)
> > vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
> > @@ -7541,7 +7541,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
> > void intel_dp_get_m_n(struct intel_crtc *crtc,
> > struct intel_crtc_state *pipe_config)
> > {
> > - if (crtc->config.has_pch_encoder)
> > + if (pipe_config->has_pch_encoder)
>
> I think this one might also change the semantics? The callchain
>
> check_crtc_state() -> intel_{dp,ddi}_get_config() -> intel_dp_get_m_n()
>
> passes down a fresh pipe_config() that isn't the same structure stored
> in crtc->config (although it hopefully has the same values in the end).
This looks like a straight up bug fix to me. Apparently I already
fumbled it when I introduced the DP M/N readout.
The state checker hasn't tripped on this since we've already
written the new pipe config to crtc->config by the time we do the
readout during modeset.
And intel_modeset_readout_hw_state() reads the state directly into
crtc->config, so even the initial state would have come out correct.
So, while the code is wrong, doesn't look like it could have caused
any real issues.
>
>
> Matt
>
> > intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
> > else
> > intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 4/8] drm/i915: Use local pipe_config varariable when available
2014-12-15 19:21 ` Ville Syrjälä
@ 2014-12-16 9:25 ` Daniel Vetter
0 siblings, 0 replies; 20+ messages in thread
From: Daniel Vetter @ 2014-12-16 9:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Ander Conselvan de Oliveira, intel-gfx, shuang.he
On Mon, Dec 15, 2014 at 09:21:41PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 15, 2014 at 10:37:57AM -0800, Matt Roper wrote:
> > On Thu, Dec 11, 2014 at 02:38:07PM +0200, Ander Conselvan de Oliveira wrote:
> > > @@ -7541,7 +7541,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
> > > void intel_dp_get_m_n(struct intel_crtc *crtc,
> > > struct intel_crtc_state *pipe_config)
> > > {
> > > - if (crtc->config.has_pch_encoder)
> > > + if (pipe_config->has_pch_encoder)
> >
> > I think this one might also change the semantics? The callchain
> >
> > check_crtc_state() -> intel_{dp,ddi}_get_config() -> intel_dp_get_m_n()
> >
> > passes down a fresh pipe_config() that isn't the same structure stored
> > in crtc->config (although it hopefully has the same values in the end).
>
> This looks like a straight up bug fix to me. Apparently I already
> fumbled it when I introduced the DP M/N readout.
>
> The state checker hasn't tripped on this since we've already
> written the new pipe config to crtc->config by the time we do the
> readout during modeset.
>
> And intel_modeset_readout_hw_state() reads the state directly into
> crtc->config, so even the initial state would have come out correct.
>
> So, while the code is wrong, doesn't look like it could have caused
> any real issues.
We also have very light coverage of direct modeset changes (i.e. without
going through off in-between). Iirc most of the igts shut down stuff in
between before setting the new modes (because that's the only way to get
somewhat reliably modesets without atomic updates). I think we should
expect more fun in this area once we have real atomic modesets.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()
2014-12-11 12:38 [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync Ander Conselvan de Oliveira
` (3 preceding siblings ...)
2014-12-11 12:38 ` [PATCH 4/8] drm/i915: Use local pipe_config varariable when available Ander Conselvan de Oliveira
@ 2014-12-11 12:38 ` Ander Conselvan de Oliveira
2014-12-15 19:17 ` Matt Roper
2014-12-15 19:24 ` Ville Syrjälä
2014-12-11 12:38 ` [PATCH 6/8] drm/i915: Remove intel_crtc->new_config pointer Ander Conselvan de Oliveira
` (2 subsequent siblings)
7 siblings, 2 replies; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-11 12:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, shuang.he
So that we can get rid of the new_config pointer later.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++--------
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index da5af23..a9f3034 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4897,27 +4897,39 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
}
/* compute the max pixel clock for new configuration */
-static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
+static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
+ struct intel_crtc *mode_set_crtc,
+ struct intel_crtc_state *crtc_new_state)
{
struct drm_device *dev = dev_priv->dev;
struct intel_crtc *intel_crtc;
int max_pixclk = 0;
+ int pixclk;
for_each_intel_crtc(dev, intel_crtc) {
- if (intel_crtc->new_enabled)
- max_pixclk = max(max_pixclk,
- intel_crtc->new_config->base.adjusted_mode.crtc_clock);
+ if (!intel_crtc->new_enabled)
+ continue;
+
+ if (intel_crtc == mode_set_crtc)
+ pixclk = crtc_new_state->base.adjusted_mode.crtc_clock;
+ else
+ pixclk = intel_crtc->config->base.adjusted_mode.crtc_clock;
+
+ max_pixclk = max(max_pixclk, pixclk);
}
return max_pixclk;
}
static void valleyview_modeset_global_pipes(struct drm_device *dev,
- unsigned *prepare_pipes)
+ unsigned *prepare_pipes,
+ struct intel_crtc *mode_set_crtc,
+ struct intel_crtc_state *crtc_new_state)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc;
- int max_pixclk = intel_mode_max_pixclk(dev_priv);
+ int max_pixclk =
+ intel_mode_max_pixclk(dev_priv, mode_set_crtc, crtc_new_state);
if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
dev_priv->vlv_cdclk_freq)
@@ -4932,7 +4944,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
static void valleyview_modeset_global_resources(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- int max_pixclk = intel_mode_max_pixclk(dev_priv);
+ int max_pixclk = intel_mode_max_pixclk(dev_priv, NULL, NULL);
int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
if (req_cdclk != dev_priv->vlv_cdclk_freq) {
@@ -10956,7 +10968,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
* adjusted_mode bits in the crtc directly.
*/
if (IS_VALLEYVIEW(dev)) {
- valleyview_modeset_global_pipes(dev, &prepare_pipes);
+ valleyview_modeset_global_pipes(dev, &prepare_pipes,
+ to_intel_crtc(crtc),
+ pipe_config);
/* may have added more to prepare_pipes than we should */
prepare_pipes &= ~disable_pipes;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()
2014-12-11 12:38 ` [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk() Ander Conselvan de Oliveira
@ 2014-12-15 19:17 ` Matt Roper
2014-12-15 19:30 ` Ville Syrjälä
2014-12-15 19:24 ` Ville Syrjälä
1 sibling, 1 reply; 20+ messages in thread
From: Matt Roper @ 2014-12-15 19:17 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx, shuang.he
On Thu, Dec 11, 2014 at 02:38:08PM +0200, Ander Conselvan de Oliveira wrote:
> So that we can get rid of the new_config pointer later.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++--------
> 1 file changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index da5af23..a9f3034 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4897,27 +4897,39 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> }
>
> /* compute the max pixel clock for new configuration */
> -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
> + struct intel_crtc *mode_set_crtc,
I'm not sure if you need to pass this. drm_crtc_state has a backpointer
to the corresponding drm_crtc now, so if we ensure that's set by our
driver when creating a new pipe_config, we could probably get away with
just passing the state here.
> + struct intel_crtc_state *crtc_new_state)
> {
> struct drm_device *dev = dev_priv->dev;
> struct intel_crtc *intel_crtc;
> int max_pixclk = 0;
> + int pixclk;
>
> for_each_intel_crtc(dev, intel_crtc) {
> - if (intel_crtc->new_enabled)
> - max_pixclk = max(max_pixclk,
> - intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> + if (!intel_crtc->new_enabled)
> + continue;
Not really related to this patch specifically, but I'm a little fuzzy on
the distinction between drm_crtc->enabled and drm_crtc_state->enable
(and then by extension intel_crtc->new_enabled). It's not immediately
clear to me why we can't just have a single 'enabled' in the base state
structure and then when we have a new config that we're passing around,
the enabled flag in that structure would serve the purpose that
intel_crtc->new_enabled does for i915 today. I'm probably
misunderstanding something.
Matt
> +
> + if (intel_crtc == mode_set_crtc)
> + pixclk = crtc_new_state->base.adjusted_mode.crtc_clock;
> + else
> + pixclk = intel_crtc->config->base.adjusted_mode.crtc_clock;
> +
> + max_pixclk = max(max_pixclk, pixclk);
> }
>
> return max_pixclk;
> }
>
> static void valleyview_modeset_global_pipes(struct drm_device *dev,
> - unsigned *prepare_pipes)
> + unsigned *prepare_pipes,
> + struct intel_crtc *mode_set_crtc,
> + struct intel_crtc_state *crtc_new_state)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc;
> - int max_pixclk = intel_mode_max_pixclk(dev_priv);
> + int max_pixclk =
> + intel_mode_max_pixclk(dev_priv, mode_set_crtc, crtc_new_state);
>
> if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> dev_priv->vlv_cdclk_freq)
> @@ -4932,7 +4944,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
> static void valleyview_modeset_global_resources(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int max_pixclk = intel_mode_max_pixclk(dev_priv);
> + int max_pixclk = intel_mode_max_pixclk(dev_priv, NULL, NULL);
> int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
>
> if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> @@ -10956,7 +10968,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> * adjusted_mode bits in the crtc directly.
> */
> if (IS_VALLEYVIEW(dev)) {
> - valleyview_modeset_global_pipes(dev, &prepare_pipes);
> + valleyview_modeset_global_pipes(dev, &prepare_pipes,
> + to_intel_crtc(crtc),
> + pipe_config);
>
> /* may have added more to prepare_pipes than we should */
> prepare_pipes &= ~disable_pipes;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()
2014-12-15 19:17 ` Matt Roper
@ 2014-12-15 19:30 ` Ville Syrjälä
2014-12-16 9:29 ` Daniel Vetter
0 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjälä @ 2014-12-15 19:30 UTC (permalink / raw)
To: Matt Roper; +Cc: Ander Conselvan de Oliveira, intel-gfx, shuang.he
On Mon, Dec 15, 2014 at 11:17:45AM -0800, Matt Roper wrote:
> On Thu, Dec 11, 2014 at 02:38:08PM +0200, Ander Conselvan de Oliveira wrote:
> > So that we can get rid of the new_config pointer later.
> >
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++--------
> > 1 file changed, 22 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index da5af23..a9f3034 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4897,27 +4897,39 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> > }
> >
> > /* compute the max pixel clock for new configuration */
> > -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> > +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
> > + struct intel_crtc *mode_set_crtc,
>
> I'm not sure if you need to pass this. drm_crtc_state has a backpointer
> to the corresponding drm_crtc now, so if we ensure that's set by our
> driver when creating a new pipe_config, we could probably get away with
> just passing the state here.
>
> > + struct intel_crtc_state *crtc_new_state)
> > {
> > struct drm_device *dev = dev_priv->dev;
> > struct intel_crtc *intel_crtc;
> > int max_pixclk = 0;
> > + int pixclk;
> >
> > for_each_intel_crtc(dev, intel_crtc) {
> > - if (intel_crtc->new_enabled)
> > - max_pixclk = max(max_pixclk,
> > - intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> > + if (!intel_crtc->new_enabled)
> > + continue;
>
> Not really related to this patch specifically, but I'm a little fuzzy on
> the distinction between drm_crtc->enabled and drm_crtc_state->enable
> (and then by extension intel_crtc->new_enabled). It's not immediately
> clear to me why we can't just have a single 'enabled' in the base state
> structure and then when we have a new config that we're passing around,
> the enabled flag in that structure would serve the purpose that
> intel_crtc->new_enabled does for i915 today. I'm probably
> misunderstanding something.
Yeah that sounds like where we want to go. No more random bits of
state sprinkled all over the place, and instead have it all neatly
collected in the state struct.
>
>
> Matt
>
> > +
> > + if (intel_crtc == mode_set_crtc)
> > + pixclk = crtc_new_state->base.adjusted_mode.crtc_clock;
> > + else
> > + pixclk = intel_crtc->config->base.adjusted_mode.crtc_clock;
> > +
> > + max_pixclk = max(max_pixclk, pixclk);
> > }
> >
> > return max_pixclk;
> > }
> >
> > static void valleyview_modeset_global_pipes(struct drm_device *dev,
> > - unsigned *prepare_pipes)
> > + unsigned *prepare_pipes,
> > + struct intel_crtc *mode_set_crtc,
> > + struct intel_crtc_state *crtc_new_state)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct intel_crtc *intel_crtc;
> > - int max_pixclk = intel_mode_max_pixclk(dev_priv);
> > + int max_pixclk =
> > + intel_mode_max_pixclk(dev_priv, mode_set_crtc, crtc_new_state);
> >
> > if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> > dev_priv->vlv_cdclk_freq)
> > @@ -4932,7 +4944,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
> > static void valleyview_modeset_global_resources(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > - int max_pixclk = intel_mode_max_pixclk(dev_priv);
> > + int max_pixclk = intel_mode_max_pixclk(dev_priv, NULL, NULL);
> > int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> >
> > if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> > @@ -10956,7 +10968,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> > * adjusted_mode bits in the crtc directly.
> > */
> > if (IS_VALLEYVIEW(dev)) {
> > - valleyview_modeset_global_pipes(dev, &prepare_pipes);
> > + valleyview_modeset_global_pipes(dev, &prepare_pipes,
> > + to_intel_crtc(crtc),
> > + pipe_config);
> >
> > /* may have added more to prepare_pipes than we should */
> > prepare_pipes &= ~disable_pipes;
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()
2014-12-15 19:30 ` Ville Syrjälä
@ 2014-12-16 9:29 ` Daniel Vetter
0 siblings, 0 replies; 20+ messages in thread
From: Daniel Vetter @ 2014-12-16 9:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Ander Conselvan de Oliveira, intel-gfx, shuang.he
On Mon, Dec 15, 2014 at 09:30:44PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 15, 2014 at 11:17:45AM -0800, Matt Roper wrote:
> > Not really related to this patch specifically, but I'm a little fuzzy on
> > the distinction between drm_crtc->enabled and drm_crtc_state->enable
> > (and then by extension intel_crtc->new_enabled). It's not immediately
> > clear to me why we can't just have a single 'enabled' in the base state
> > structure and then when we have a new config that we're passing around,
> > the enabled flag in that structure would serve the purpose that
> > intel_crtc->new_enabled does for i915 today. I'm probably
> > misunderstanding something.
>
> Yeah that sounds like where we want to go. No more random bits of
> state sprinkled all over the place, and instead have it all neatly
> collected in the state struct.
Yeah, that's the plane. I don't think we can get rid of ->new_config and
->config though since conceptually for async updates we need to commit the
sw side synchronously (so that the next atomic update is relative to the
currently scheduled state update). But internally in the driver backend we
need to still have the staging and only update once all the things from
the old state have been shut down.
But everything else should just go in there.
The other problem is other drivers not yet converted to atomic. Until we
have those we can't get rid of duplicated state variables in core drm
structs. But as soon as i915 is fully converted we can forget about them,
since then helpers will update those for us. Or at least should - we might
need to move§ some code from the atomic helpers used only by drivers
with crtc helper hooks to make that work correctly and put it into core
code.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()
2014-12-11 12:38 ` [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk() Ander Conselvan de Oliveira
2014-12-15 19:17 ` Matt Roper
@ 2014-12-15 19:24 ` Ville Syrjälä
2014-12-16 9:34 ` Daniel Vetter
1 sibling, 1 reply; 20+ messages in thread
From: Ville Syrjälä @ 2014-12-15 19:24 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx, shuang.he
On Thu, Dec 11, 2014 at 02:38:08PM +0200, Ander Conselvan de Oliveira wrote:
> So that we can get rid of the new_config pointer later.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++--------
> 1 file changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index da5af23..a9f3034 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4897,27 +4897,39 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> }
>
> /* compute the max pixel clock for new configuration */
> -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
> + struct intel_crtc *mode_set_crtc,
> + struct intel_crtc_state *crtc_new_state)
> {
> struct drm_device *dev = dev_priv->dev;
> struct intel_crtc *intel_crtc;
> int max_pixclk = 0;
> + int pixclk;
>
> for_each_intel_crtc(dev, intel_crtc) {
> - if (intel_crtc->new_enabled)
> - max_pixclk = max(max_pixclk,
> - intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> + if (!intel_crtc->new_enabled)
> + continue;
> +
> + if (intel_crtc == mode_set_crtc)
> + pixclk = crtc_new_state->base.adjusted_mode.crtc_clock;
> + else
> + pixclk = intel_crtc->config->base.adjusted_mode.crtc_clock;
> +
> + max_pixclk = max(max_pixclk, pixclk);
I think we're now going backwards. We want atomic modesets, so we
need to be able to compute this stuff when modesetting multiple pipes.
That was precisely why I added new_config.
> }
>
> return max_pixclk;
> }
>
> static void valleyview_modeset_global_pipes(struct drm_device *dev,
> - unsigned *prepare_pipes)
> + unsigned *prepare_pipes,
> + struct intel_crtc *mode_set_crtc,
> + struct intel_crtc_state *crtc_new_state)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc;
> - int max_pixclk = intel_mode_max_pixclk(dev_priv);
> + int max_pixclk =
> + intel_mode_max_pixclk(dev_priv, mode_set_crtc, crtc_new_state);
>
> if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> dev_priv->vlv_cdclk_freq)
> @@ -4932,7 +4944,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
> static void valleyview_modeset_global_resources(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int max_pixclk = intel_mode_max_pixclk(dev_priv);
> + int max_pixclk = intel_mode_max_pixclk(dev_priv, NULL, NULL);
> int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
>
> if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> @@ -10956,7 +10968,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> * adjusted_mode bits in the crtc directly.
> */
> if (IS_VALLEYVIEW(dev)) {
> - valleyview_modeset_global_pipes(dev, &prepare_pipes);
> + valleyview_modeset_global_pipes(dev, &prepare_pipes,
> + to_intel_crtc(crtc),
> + pipe_config);
>
> /* may have added more to prepare_pipes than we should */
> prepare_pipes &= ~disable_pipes;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()
2014-12-15 19:24 ` Ville Syrjälä
@ 2014-12-16 9:34 ` Daniel Vetter
2014-12-18 15:06 ` Ander Conselvan de Oliveira
0 siblings, 1 reply; 20+ messages in thread
From: Daniel Vetter @ 2014-12-16 9:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Ander Conselvan de Oliveira, intel-gfx, shuang.he
On Mon, Dec 15, 2014 at 09:24:23PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 11, 2014 at 02:38:08PM +0200, Ander Conselvan de Oliveira wrote:
> > So that we can get rid of the new_config pointer later.
> >
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++--------
> > 1 file changed, 22 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index da5af23..a9f3034 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4897,27 +4897,39 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> > }
> >
> > /* compute the max pixel clock for new configuration */
> > -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> > +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
> > + struct intel_crtc *mode_set_crtc,
> > + struct intel_crtc_state *crtc_new_state)
> > {
> > struct drm_device *dev = dev_priv->dev;
> > struct intel_crtc *intel_crtc;
> > int max_pixclk = 0;
> > + int pixclk;
> >
> > for_each_intel_crtc(dev, intel_crtc) {
> > - if (intel_crtc->new_enabled)
> > - max_pixclk = max(max_pixclk,
> > - intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> > + if (!intel_crtc->new_enabled)
> > + continue;
> > +
> > + if (intel_crtc == mode_set_crtc)
> > + pixclk = crtc_new_state->base.adjusted_mode.crtc_clock;
> > + else
> > + pixclk = intel_crtc->config->base.adjusted_mode.crtc_clock;
> > +
> > + max_pixclk = max(max_pixclk, pixclk);
>
> I think we're now going backwards. We want atomic modesets, so we
> need to be able to compute this stuff when modesetting multiple pipes.
> That was precisely why I added new_config.
We've already started going backwards in this area with the latest round
of fastboot patches from Jesse. I've discussed this a bit with him and the
plan is that we'll do it that way and Ander gets shafted^W signed up to
sort out the mess.
But yeah if there's a shortcut to avoid some of that detour it would be
good.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()
2014-12-16 9:34 ` Daniel Vetter
@ 2014-12-18 15:06 ` Ander Conselvan de Oliveira
0 siblings, 0 replies; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-18 15:06 UTC (permalink / raw)
To: Daniel Vetter, Ville Syrjälä
Cc: Ander Conselvan de Oliveira, intel-gfx, shuang.he
On 16-12-2014 11:34, Daniel Vetter wrote:
> On Mon, Dec 15, 2014 at 09:24:23PM +0200, Ville Syrjälä wrote:
>> On Thu, Dec 11, 2014 at 02:38:08PM +0200, Ander Conselvan de Oliveira wrote:
>>> So that we can get rid of the new_config pointer later.
>>>
>>> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++--------
>>> 1 file changed, 22 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index da5af23..a9f3034 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -4897,27 +4897,39 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>>> }
>>>
>>> /* compute the max pixel clock for new configuration */
>>> -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
>>> +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
>>> + struct intel_crtc *mode_set_crtc,
>>> + struct intel_crtc_state *crtc_new_state)
>>> {
>>> struct drm_device *dev = dev_priv->dev;
>>> struct intel_crtc *intel_crtc;
>>> int max_pixclk = 0;
>>> + int pixclk;
>>>
>>> for_each_intel_crtc(dev, intel_crtc) {
>>> - if (intel_crtc->new_enabled)
>>> - max_pixclk = max(max_pixclk,
>>> - intel_crtc->new_config->base.adjusted_mode.crtc_clock);
>>> + if (!intel_crtc->new_enabled)
>>> + continue;
>>> +
>>> + if (intel_crtc == mode_set_crtc)
>>> + pixclk = crtc_new_state->base.adjusted_mode.crtc_clock;
>>> + else
>>> + pixclk = intel_crtc->config->base.adjusted_mode.crtc_clock;
>>> +
>>> + max_pixclk = max(max_pixclk, pixclk);
>>
>> I think we're now going backwards. We want atomic modesets, so we
>> need to be able to compute this stuff when modesetting multiple pipes.
>> That was precisely why I added new_config.
>
> We've already started going backwards in this area with the latest round
> of fastboot patches from Jesse. I've discussed this a bit with him and the
> plan is that we'll do it that way and Ander gets shafted^W signed up to
> sort out the mess.
>
> But yeah if there's a shortcut to avoid some of that detour it would be
> good.
I should improve the commit message. I agree this patch is a step
backwards, but the idea is to move stuff out of the way so we can move
forwards again. The ultimate goal is to pass a drm_atomic_state struct,
and derive the pipe_config from that.
Ander
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 6/8] drm/i915: Remove intel_crtc->new_config pointer
2014-12-11 12:38 [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync Ander Conselvan de Oliveira
` (4 preceding siblings ...)
2014-12-11 12:38 ` [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk() Ander Conselvan de Oliveira
@ 2014-12-11 12:38 ` Ander Conselvan de Oliveira
2014-12-11 12:38 ` [PATCH 7/8] drm/i915: Make intel_crtc->config a pointer Ander Conselvan de Oliveira
2014-12-11 12:38 ` [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config Ander Conselvan de Oliveira
7 siblings, 0 replies; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-11 12:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, shuang.he
There are no more users of that pointer since the new config is now
passed down the call chain during mode set. Also, when the switch to
atomic happens, the right config (state) should be derived from an
atomic state structure.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 46 ++++++++----------------------------
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 10 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a9f3034..a032a1d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8583,7 +8583,6 @@ retry:
intel_crtc = to_intel_crtc(crtc);
intel_crtc->new_enabled = true;
- intel_crtc->new_config = &intel_crtc->config;
old->dpms_mode = connector->dpms;
old->load_detect_temp = true;
old->release_fb = NULL;
@@ -8623,10 +8622,6 @@ retry:
fail:
intel_crtc->new_enabled = crtc->enabled;
- if (intel_crtc->new_enabled)
- intel_crtc->new_config = &intel_crtc->config;
- else
- intel_crtc->new_config = NULL;
fail_unlock:
if (ret == -EDEADLK) {
drm_modeset_backoff(ctx);
@@ -8653,7 +8648,6 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
to_intel_connector(connector)->new_encoder = NULL;
intel_encoder->new_crtc = NULL;
intel_crtc->new_enabled = false;
- intel_crtc->new_config = NULL;
intel_set_mode(crtc, NULL, 0, 0, NULL);
if (old->release_fb) {
@@ -9839,14 +9833,8 @@ static void intel_modeset_update_staged_output_state(struct drm_device *dev)
to_intel_crtc(encoder->base.crtc);
}
- for_each_intel_crtc(dev, crtc) {
+ for_each_intel_crtc(dev, crtc)
crtc->new_enabled = crtc->base.enabled;
-
- if (crtc->new_enabled)
- crtc->new_config = &crtc->config;
- else
- crtc->new_config = NULL;
- }
}
/**
@@ -10355,12 +10343,8 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
intel_modeset_commit_output_state(dev);
/* Double check state. */
- for_each_intel_crtc(dev, intel_crtc) {
+ for_each_intel_crtc(dev, intel_crtc)
WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
- WARN_ON(intel_crtc->new_config &&
- intel_crtc->new_config != &intel_crtc->config);
- WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
- }
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
if (!connector->encoder || !connector->encoder->crtc)
@@ -10957,9 +10941,6 @@ static int __intel_set_mode(struct drm_crtc *crtc,
*saved_mode = crtc->mode;
- if (modeset_pipes)
- to_intel_crtc(crtc)->new_config = pipe_config;
-
/*
* See if the config requires any additional preparation, e.g.
* to adjust global state with pipes off. We need to do this
@@ -10984,7 +10965,13 @@ static int __intel_set_mode(struct drm_crtc *crtc,
goto done;
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
- struct intel_crtc_state *state = intel_crtc->new_config;
+ struct intel_crtc_state *state;
+
+ if (&intel_crtc->base == crtc)
+ state = pipe_config;
+ else
+ state = intel_crtc->config;
+
ret = dev_priv->display.crtc_compute_clock(intel_crtc,
state);
if (ret) {
@@ -11014,7 +11001,6 @@ static int __intel_set_mode(struct drm_crtc *crtc,
/* mode_set/enable/disable functions rely on a correct pipe
* config. */
to_intel_crtc(crtc)->config = *pipe_config;
- to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
/*
* Calculate and store various constants which
@@ -11177,15 +11163,9 @@ static void intel_set_config_restore_state(struct drm_device *dev,
int count;
count = 0;
- for_each_intel_crtc(dev, crtc) {
+ for_each_intel_crtc(dev, crtc)
crtc->new_enabled = config->save_crtc_enabled[count++];
- if (crtc->new_enabled)
- crtc->new_config = &crtc->config;
- else
- crtc->new_config = NULL;
- }
-
count = 0;
for_each_intel_encoder(dev, encoder) {
encoder->new_crtc =
@@ -11391,11 +11371,6 @@ intel_modeset_stage_output_state(struct drm_device *dev,
crtc->new_enabled ? "en" : "dis");
config->mode_changed = true;
}
-
- if (crtc->new_enabled)
- crtc->new_config = &crtc->config;
- else
- crtc->new_config = NULL;
}
return 0;
@@ -11422,7 +11397,6 @@ static void disable_crtc_nofb(struct intel_crtc *crtc)
}
crtc->new_enabled = false;
- crtc->new_config = NULL;
}
static int intel_crtc_set_config(struct drm_mode_set *set)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0a84667..175b853 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -440,7 +440,6 @@ struct intel_crtc {
struct intel_plane_config plane_config;
struct intel_crtc_state config;
- struct intel_crtc_state *new_config;
bool new_enabled;
/* reset counter value when the last flip was submitted */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 7/8] drm/i915: Make intel_crtc->config a pointer
2014-12-11 12:38 [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync Ander Conselvan de Oliveira
` (5 preceding siblings ...)
2014-12-11 12:38 ` [PATCH 6/8] drm/i915: Remove intel_crtc->new_config pointer Ander Conselvan de Oliveira
@ 2014-12-11 12:38 ` Ander Conselvan de Oliveira
2014-12-15 19:30 ` Matt Roper
2014-12-11 12:38 ` [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config Ander Conselvan de Oliveira
7 siblings, 1 reply; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-11 12:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, shuang.he
To match the semantics of drm_crtc->state, which this will eventually
become.
@@ struct intel_crtc *crtc; @@
-&crtc->config
+crtc->config
@@ struct intel_crtc *crtc; identifier member; @@
-crtc->config.member
+crtc->config->member
@@ struct drm_crtc *crtc; @@
-&to_intel_crtc(crtc)->config
+to_intel_crtc(crtc)->config
@@ struct drm_crtc *crtc; identifier member; @@
-to_intel_crtc(crtc)->config.member
+to_intel_crtc(crtc)->config->member
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +-
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/intel_audio.c | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 52 +++----
drivers/gpu/drm/i915/intel_display.c | 275 ++++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_dp.c | 16 +-
drivers/gpu/drm/i915/intel_dp_mst.c | 7 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 8 +-
drivers/gpu/drm/i915/intel_dvo.c | 8 +-
drivers/gpu/drm/i915/intel_fbdev.c | 10 +-
drivers/gpu/drm/i915/intel_hdmi.c | 36 ++---
drivers/gpu/drm/i915/intel_lvds.c | 6 +-
drivers/gpu/drm/i915/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 56 +++----
drivers/gpu/drm/i915/intel_psr.c | 8 +-
drivers/gpu/drm/i915/intel_sdvo.c | 14 +-
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
19 files changed, 270 insertions(+), 256 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d0e445e..a724e8c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2572,7 +2572,7 @@ static int i915_display_info(struct seq_file *m, void *unused)
seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
crtc->base.base.id, pipe_name(crtc->pipe),
- yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
+ yesno(crtc->active), crtc->config->pipe_src_w, crtc->config->pipe_src_h);
if (crtc->active) {
intel_crtc_info(m, crtc);
@@ -3280,9 +3280,9 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
* relevant on hsw with pipe A when using the always-on power well
* routing.
*/
- if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
- !crtc->config.pch_pfit.enabled) {
- crtc->config.pch_pfit.force_thru = true;
+ if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
+ !crtc->config->pch_pfit.enabled) {
+ crtc->config->pch_pfit.force_thru = true;
intel_display_power_get(dev_priv,
POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
@@ -3306,8 +3306,8 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
* relevant on hsw with pipe A when using the always-on power well
* routing.
*/
- if (crtc->config.pch_pfit.force_thru) {
- crtc->config.pch_pfit.force_thru = false;
+ if (crtc->config->pch_pfit.force_thru) {
+ crtc->config->pch_pfit.force_thru = false;
dev_priv->display.crtc_disable(&crtc->base);
dev_priv->display.crtc_enable(&crtc->base);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 11e209e..e55b275 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -567,7 +567,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
struct intel_crtc *intel_crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
const struct drm_display_mode *mode =
- &intel_crtc->config.base.adjusted_mode;
+ &intel_crtc->config->base.adjusted_mode;
htotal = mode->crtc_htotal;
hsync_start = mode->crtc_hsync_start;
@@ -638,7 +638,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
+ const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
enum pipe pipe = crtc->pipe;
int position, vtotal;
@@ -665,7 +665,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- const struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
+ const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
bool in_vbl = true;
@@ -823,7 +823,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
vblank_time, flags,
crtc,
- &to_intel_crtc(crtc)->config.base.adjusted_mode);
+ &to_intel_crtc(crtc)->config->base.adjusted_mode);
}
static bool intel_hpd_irq_event(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index fe8c496..e84a798 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -397,7 +397,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
{
struct drm_encoder *encoder = &intel_encoder->base;
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
- struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
+ struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
struct drm_connector *connector;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index e4f6d49..bb55368 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -157,7 +157,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crt *crt = intel_encoder_to_crt(encoder);
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
u32 adpa;
if (INTEL_INFO(dev)->gen >= 5)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 970ca30..c409ccc 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -328,7 +328,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
/* Enable the PCH Receiver FDI PLL */
rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
FDI_RX_PLL_ENABLE |
- FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
+ FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
POSTING_READ(_FDI_RXA_CTL);
udelay(220);
@@ -338,8 +338,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
/* Configure Port Clock Select */
- I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
- WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
+ I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
+ WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
/* Start the training iterating through available voltages and emphasis,
* testing each value twice. */
@@ -357,7 +357,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
* port reversal bit */
I915_WRITE(DDI_BUF_CTL(PORT_E),
DDI_BUF_CTL_ENABLE |
- ((intel_crtc->config.fdi_lanes - 1) << 1) |
+ ((intel_crtc->config->fdi_lanes - 1) << 1) |
DDI_BUF_TRANS_SELECT(i / 2));
POSTING_READ(DDI_BUF_CTL(PORT_E));
@@ -1186,13 +1186,13 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
int type = intel_encoder->type;
uint32_t temp;
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
temp = TRANS_MSA_SYNC_CLK;
- switch (intel_crtc->config.pipe_bpp) {
+ switch (intel_crtc->config->pipe_bpp) {
case 18:
temp |= TRANS_MSA_6_BPC;
break;
@@ -1217,7 +1217,7 @@ void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
uint32_t temp;
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (state == true)
@@ -1235,7 +1235,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe = intel_crtc->pipe;
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
int type = intel_encoder->type;
uint32_t temp;
@@ -1244,7 +1244,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
temp = TRANS_DDI_FUNC_ENABLE;
temp |= TRANS_DDI_SELECT_PORT(port);
- switch (intel_crtc->config.pipe_bpp) {
+ switch (intel_crtc->config->pipe_bpp) {
case 18:
temp |= TRANS_DDI_BPC_6;
break;
@@ -1261,9 +1261,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
BUG();
}
- if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
+ if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
temp |= TRANS_DDI_PVSYNC;
- if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
+ if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
temp |= TRANS_DDI_PHSYNC;
if (cpu_transcoder == TRANSCODER_EDP) {
@@ -1274,8 +1274,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
* using motion blur mitigation (which we don't
* support). */
if (IS_HASWELL(dev) &&
- (intel_crtc->config.pch_pfit.enabled ||
- intel_crtc->config.pch_pfit.force_thru))
+ (intel_crtc->config->pch_pfit.enabled ||
+ intel_crtc->config->pch_pfit.force_thru))
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
else
temp |= TRANS_DDI_EDP_INPUT_A_ON;
@@ -1293,14 +1293,14 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
}
if (type == INTEL_OUTPUT_HDMI) {
- if (intel_crtc->config.has_hdmi_sink)
+ if (intel_crtc->config->has_hdmi_sink)
temp |= TRANS_DDI_MODE_SELECT_HDMI;
else
temp |= TRANS_DDI_MODE_SELECT_DVI;
} else if (type == INTEL_OUTPUT_ANALOG) {
temp |= TRANS_DDI_MODE_SELECT_FDI;
- temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
+ temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
type == INTEL_OUTPUT_EDP) {
@@ -1450,7 +1450,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
@@ -1460,7 +1460,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
@@ -1482,7 +1482,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
}
if (IS_SKYLAKE(dev)) {
- uint32_t dpll = crtc->config.ddi_pll_sel;
+ uint32_t dpll = crtc->config->ddi_pll_sel;
uint32_t val;
/*
@@ -1497,7 +1497,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
DPLL_CTRL1_SSC(dpll) |
DPLL_CRTL1_LINK_RATE_MASK(dpll));
- val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6);
+ val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
I915_WRITE(DPLL_CTRL1, val);
POSTING_READ(DPLL_CTRL1);
@@ -1514,8 +1514,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
I915_WRITE(DPLL_CTRL2, val);
} else {
- WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
- I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
+ WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
+ I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
}
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
@@ -1532,8 +1532,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
intel_hdmi->set_infoframes(encoder,
- crtc->config.has_hdmi_sink,
- &crtc->config.base.adjusted_mode);
+ crtc->config->has_hdmi_sink,
+ &crtc->config->base.adjusted_mode);
}
}
@@ -1607,7 +1607,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
intel_psr_enable(intel_dp);
}
- if (intel_crtc->config.has_audio) {
+ if (intel_crtc->config->has_audio) {
intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
intel_audio_codec_enable(intel_encoder);
}
@@ -1622,7 +1622,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (intel_crtc->config.has_audio) {
+ if (intel_crtc->config->has_audio) {
intel_audio_codec_disable(intel_encoder);
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
}
@@ -2031,7 +2031,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
struct intel_hdmi *intel_hdmi;
u32 temp, flags = 0;
struct drm_device *dev = dev_priv->dev;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a032a1d..462f22a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -895,7 +895,7 @@ bool intel_crtc_active(struct drm_crtc *crtc)
* properly reconstruct framebuffers.
*/
return intel_crtc->active && crtc->primary->fb &&
- intel_crtc->config.base.adjusted_mode.crtc_clock;
+ intel_crtc->config->base.adjusted_mode.crtc_clock;
}
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -904,7 +904,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- return intel_crtc->config.cpu_transcoder;
+ return intel_crtc->config->cpu_transcoder;
}
static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
@@ -946,7 +946,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
enum pipe pipe = crtc->pipe;
if (INTEL_INFO(dev)->gen >= 4) {
@@ -1052,10 +1052,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
- if (crtc->config.shared_dpll < 0)
+ if (crtc->config->shared_dpll < 0)
return NULL;
- return &dev_priv->shared_dplls[crtc->config.shared_dpll];
+ return &dev_priv->shared_dplls[crtc->config->shared_dpll];
}
/* For ILK+ */
@@ -1599,7 +1599,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
int reg = DPLL(crtc->pipe);
- u32 dpll = crtc->config.dpll_hw_state.dpll;
+ u32 dpll = crtc->config->dpll_hw_state.dpll;
assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -1629,7 +1629,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
if (INTEL_INFO(dev)->gen >= 4) {
I915_WRITE(DPLL_MD(crtc->pipe),
- crtc->config.dpll_hw_state.dpll_md);
+ crtc->config->dpll_hw_state.dpll_md);
} else {
/* The pixel multiplier can only be updated once the
* DPLL is enabled and the clocks are stable.
@@ -2034,7 +2034,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
else
assert_pll_enabled(dev_priv, pipe);
else {
- if (crtc->config.has_pch_encoder) {
+ if (crtc->config->has_pch_encoder) {
/* if driving the PCH, we need FDI enabled */
assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
assert_fdi_tx_pll_enabled(dev_priv,
@@ -2068,7 +2068,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
static void intel_disable_pipe(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
- enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
enum pipe pipe = crtc->pipe;
int reg;
u32 val;
@@ -2090,7 +2090,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
* Double wide has implications for planes
* so best keep it disabled when not needed.
*/
- if (crtc->config.double_wide)
+ if (crtc->config->double_wide)
val &= ~PIPECONF_DOUBLE_WIDE;
/* Don't disable pipe or pipe PLLs if needed */
@@ -2468,13 +2468,13 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
* which should always be the user's requested size.
*/
I915_WRITE(DSPSIZE(plane),
- ((intel_crtc->config.pipe_src_h - 1) << 16) |
- (intel_crtc->config.pipe_src_w - 1));
+ ((intel_crtc->config->pipe_src_h - 1) << 16) |
+ (intel_crtc->config->pipe_src_w - 1));
I915_WRITE(DSPPOS(plane), 0);
} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
I915_WRITE(PRIMSIZE(plane),
- ((intel_crtc->config.pipe_src_h - 1) << 16) |
- (intel_crtc->config.pipe_src_w - 1));
+ ((intel_crtc->config->pipe_src_h - 1) << 16) |
+ (intel_crtc->config->pipe_src_w - 1));
I915_WRITE(PRIMPOS(plane), 0);
I915_WRITE(PRIMCNSTALPHA(plane), 0);
}
@@ -2532,14 +2532,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
- x += (intel_crtc->config.pipe_src_w - 1);
- y += (intel_crtc->config.pipe_src_h - 1);
+ x += (intel_crtc->config->pipe_src_w - 1);
+ y += (intel_crtc->config->pipe_src_h - 1);
/* Finding the last pixel of the last line of the display
data and adding to linear_offset*/
linear_offset +=
- (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
- (intel_crtc->config.pipe_src_w - 1) * pixel_size;
+ (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
+ (intel_crtc->config->pipe_src_w - 1) * pixel_size;
}
I915_WRITE(reg, dspcntr);
@@ -2635,14 +2635,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
dspcntr |= DISPPLANE_ROTATE_180;
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
- x += (intel_crtc->config.pipe_src_w - 1);
- y += (intel_crtc->config.pipe_src_h - 1);
+ x += (intel_crtc->config->pipe_src_w - 1);
+ y += (intel_crtc->config->pipe_src_h - 1);
/* Finding the last pixel of the last line of the display
data and adding to linear_offset*/
linear_offset +=
- (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
- (intel_crtc->config.pipe_src_w - 1) * pixel_size;
+ (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
+ (intel_crtc->config->pipe_src_w - 1) * pixel_size;
}
}
@@ -2741,8 +2741,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
I915_WRITE(PLANE_POS(pipe, 0), 0);
I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
I915_WRITE(PLANE_SIZE(pipe, 0),
- (intel_crtc->config.pipe_src_h - 1) << 16 |
- (intel_crtc->config.pipe_src_w - 1));
+ (intel_crtc->config->pipe_src_h - 1) << 16 |
+ (intel_crtc->config->pipe_src_w - 1));
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
@@ -2938,20 +2938,20 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
* then update the pipesrc and pfit state, even on the flip path.
*/
- adjusted_mode = &crtc->config.base.adjusted_mode;
+ adjusted_mode = &crtc->config->base.adjusted_mode;
I915_WRITE(PIPESRC(crtc->pipe),
((adjusted_mode->crtc_hdisplay - 1) << 16) |
(adjusted_mode->crtc_vdisplay - 1));
- if (!crtc->config.pch_pfit.enabled &&
+ if (!crtc->config->pch_pfit.enabled &&
(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
I915_WRITE(PF_CTL(crtc->pipe), 0);
I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
}
- crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
- crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
+ crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
+ crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
}
static void intel_fdi_normal_train(struct drm_crtc *crtc)
@@ -2998,7 +2998,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
{
return crtc->base.enabled && crtc->active &&
- crtc->config.has_pch_encoder;
+ crtc->config->has_pch_encoder;
}
static void ivb_modeset_global_resources(struct drm_device *dev)
@@ -3053,7 +3053,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~FDI_DP_PORT_WIDTH_MASK;
- temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
+ temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_1;
I915_WRITE(reg, temp | FDI_TX_ENABLE);
@@ -3151,7 +3151,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~FDI_DP_PORT_WIDTH_MASK;
- temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
+ temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_1;
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -3302,7 +3302,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~FDI_DP_PORT_WIDTH_MASK;
- temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
+ temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
temp |= snb_b_fdi_train_param[j/2];
@@ -3390,7 +3390,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
- temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
+ temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
@@ -3574,7 +3574,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
+ int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
u32 divsel, phaseinc, auxdiv, phasedir = 0;
u32 temp;
@@ -3663,7 +3663,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
I915_READ(HTOTAL(cpu_transcoder)));
@@ -3709,7 +3709,7 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
case PIPE_A:
break;
case PIPE_B:
- if (intel_crtc->config.fdi_lanes > 2)
+ if (intel_crtc->config->fdi_lanes > 2)
WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
else
cpt_enable_fdi_bc_bifurcation(dev);
@@ -3761,7 +3761,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
temp = I915_READ(PCH_DPLL_SEL);
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
- if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
+ if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
temp |= sel;
else
temp &= ~sel;
@@ -3784,7 +3784,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
intel_fdi_normal_train(crtc);
/* For PCH DP, enable TRANS_DP_CTL */
- if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
+ if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
reg = TRANS_DP_CTL(pipe);
temp = I915_READ(reg);
@@ -3825,7 +3825,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
@@ -3855,7 +3855,7 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
WARN_ON(pll->active);
}
- crtc->config.shared_dpll = DPLL_ID_PRIVATE;
+ crtc->config->shared_dpll = DPLL_ID_PRIVATE;
}
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
@@ -4009,10 +4009,10 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = crtc->pipe;
- if (crtc->config.pch_pfit.enabled) {
+ if (crtc->config->pch_pfit.enabled) {
I915_WRITE(PS_CTL(pipe), PS_ENABLE);
- I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
- I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
+ I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
+ I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
}
}
@@ -4022,7 +4022,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = crtc->pipe;
- if (crtc->config.pch_pfit.enabled) {
+ if (crtc->config->pch_pfit.enabled) {
/* Force use of hard-coded filter coefficients
* as some pre-programmed values are broken,
* e.g. x201.
@@ -4032,8 +4032,8 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
PF_PIPE_SEL_IVB(pipe));
else
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
- I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
- I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
+ I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
+ I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
}
}
@@ -4070,7 +4070,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (!crtc->config.ips_enabled)
+ if (!crtc->config->ips_enabled)
return;
/* We can only enable IPS after we enable a plane and wait for a vblank */
@@ -4103,7 +4103,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (!crtc->config.ips_enabled)
+ if (!crtc->config->ips_enabled)
return;
assert_plane_enabled(dev_priv, crtc->plane);
@@ -4152,7 +4152,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
/* Workaround : Do not read or write the pipe palette/gamma data while
* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
*/
- if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
+ if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
GAMMA_MODE_MODE_SPLIT)) {
hsw_disable_ips(intel_crtc);
@@ -4254,17 +4254,17 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->active)
return;
- if (intel_crtc->config.has_pch_encoder)
+ if (intel_crtc->config->has_pch_encoder)
intel_prepare_shared_dpll(intel_crtc);
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config->has_dp_encoder)
intel_dp_set_m_n(intel_crtc);
intel_set_pipe_timings(intel_crtc);
- if (intel_crtc->config.has_pch_encoder) {
+ if (intel_crtc->config->has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
- &intel_crtc->config.fdi_m_n, NULL);
+ &intel_crtc->config->fdi_m_n, NULL);
}
ironlake_set_pipeconf(crtc);
@@ -4278,7 +4278,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
if (encoder->pre_enable)
encoder->pre_enable(encoder);
- if (intel_crtc->config.has_pch_encoder) {
+ if (intel_crtc->config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
* cpu pipes, hence this is separate from all the other fdi/pch
* enabling. */
@@ -4299,7 +4299,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
- if (intel_crtc->config.has_pch_encoder)
+ if (intel_crtc->config->has_pch_encoder)
ironlake_pch_enable(crtc);
for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -4365,19 +4365,19 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc_to_shared_dpll(intel_crtc))
intel_enable_shared_dpll(intel_crtc);
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config->has_dp_encoder)
intel_dp_set_m_n(intel_crtc);
intel_set_pipe_timings(intel_crtc);
- if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
- I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
- intel_crtc->config.pixel_multiplier - 1);
+ if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
+ I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
+ intel_crtc->config->pixel_multiplier - 1);
}
- if (intel_crtc->config.has_pch_encoder) {
+ if (intel_crtc->config->has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
- &intel_crtc->config.fdi_m_n, NULL);
+ &intel_crtc->config->fdi_m_n, NULL);
}
haswell_set_pipeconf(crtc);
@@ -4391,7 +4391,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
if (encoder->pre_enable)
encoder->pre_enable(encoder);
- if (intel_crtc->config.has_pch_encoder) {
+ if (intel_crtc->config->has_pch_encoder) {
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
true);
dev_priv->display.fdi_link_train(crtc);
@@ -4416,10 +4416,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
- if (intel_crtc->config.has_pch_encoder)
+ if (intel_crtc->config->has_pch_encoder)
lpt_pch_enable(crtc);
- if (intel_crtc->config.dp_encoder_is_mst)
+ if (intel_crtc->config->dp_encoder_is_mst)
intel_ddi_set_vc_payload_alloc(crtc, true);
for_each_encoder_on_crtc(dev, crtc, encoder) {
@@ -4444,7 +4444,7 @@ static void skylake_pfit_disable(struct intel_crtc *crtc)
/* To avoid upsetting the power well on haswell only disable the pfit if
* it's in use. The hw state code will make sure we get this right. */
- if (crtc->config.pch_pfit.enabled) {
+ if (crtc->config->pch_pfit.enabled) {
I915_WRITE(PS_CTL(pipe), 0);
I915_WRITE(PS_WIN_POS(pipe), 0);
I915_WRITE(PS_WIN_SZ(pipe), 0);
@@ -4459,7 +4459,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc)
/* To avoid upsetting the power well on haswell only disable the pfit if
* it's in use. The hw state code will make sure we get this right. */
- if (crtc->config.pch_pfit.enabled) {
+ if (crtc->config->pch_pfit.enabled) {
I915_WRITE(PF_CTL(pipe), 0);
I915_WRITE(PF_WIN_POS(pipe), 0);
I915_WRITE(PF_WIN_SZ(pipe), 0);
@@ -4486,7 +4486,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
for_each_encoder_on_crtc(dev, crtc, encoder)
encoder->disable(encoder);
- if (intel_crtc->config.has_pch_encoder)
+ if (intel_crtc->config->has_pch_encoder)
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
intel_disable_pipe(intel_crtc);
@@ -4497,7 +4497,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
if (encoder->post_disable)
encoder->post_disable(encoder);
- if (intel_crtc->config.has_pch_encoder) {
+ if (intel_crtc->config->has_pch_encoder) {
ironlake_fdi_disable(crtc);
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -4537,7 +4537,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
if (!intel_crtc->active)
return;
@@ -4552,12 +4552,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
encoder->disable(encoder);
}
- if (intel_crtc->config.has_pch_encoder)
+ if (intel_crtc->config->has_pch_encoder)
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
false);
intel_disable_pipe(intel_crtc);
- if (intel_crtc->config.dp_encoder_is_mst)
+ if (intel_crtc->config->dp_encoder_is_mst)
intel_ddi_set_vc_payload_alloc(crtc, false);
intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
@@ -4569,7 +4569,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
intel_ddi_disable_pipe_clock(intel_crtc);
- if (intel_crtc->config.has_pch_encoder) {
+ if (intel_crtc->config->has_pch_encoder) {
lpt_disable_pch_transcoder(dev_priv);
intel_ddi_fdi_disable(crtc);
}
@@ -4600,7 +4600,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc_state *pipe_config = &crtc->config;
+ struct intel_crtc_state *pipe_config = crtc->config;
if (!pipe_config->gmch_pfit.control)
return;
@@ -4681,8 +4681,8 @@ static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
mask = BIT(POWER_DOMAIN_PIPE(pipe));
mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
- if (intel_crtc->config.pch_pfit.enabled ||
- intel_crtc->config.pch_pfit.force_thru)
+ if (intel_crtc->config->pch_pfit.enabled ||
+ intel_crtc->config->pch_pfit.force_thru)
mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
for_each_encoder_on_crtc(dev, crtc, intel_encoder)
@@ -4986,12 +4986,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (!is_dsi) {
if (IS_CHERRYVIEW(dev))
- chv_prepare_pll(intel_crtc, &intel_crtc->config);
+ chv_prepare_pll(intel_crtc, intel_crtc->config);
else
- vlv_prepare_pll(intel_crtc, &intel_crtc->config);
+ vlv_prepare_pll(intel_crtc, intel_crtc->config);
}
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config->has_dp_encoder)
intel_dp_set_m_n(intel_crtc);
intel_set_pipe_timings(intel_crtc);
@@ -5015,9 +5015,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (!is_dsi) {
if (IS_CHERRYVIEW(dev))
- chv_enable_pll(intel_crtc, &intel_crtc->config);
+ chv_enable_pll(intel_crtc, intel_crtc->config);
else
- vlv_enable_pll(intel_crtc, &intel_crtc->config);
+ vlv_enable_pll(intel_crtc, intel_crtc->config);
}
for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -5048,8 +5048,8 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
- I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
+ I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
+ I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
}
static void i9xx_crtc_enable(struct drm_crtc *crtc)
@@ -5067,7 +5067,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
i9xx_set_pll_dividers(intel_crtc);
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config->has_dp_encoder)
intel_dp_set_m_n(intel_crtc);
intel_set_pipe_timings(intel_crtc);
@@ -5119,7 +5119,7 @@ static void i9xx_pfit_disable(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (!crtc->config.gmch_pfit.control)
+ if (!crtc->config->gmch_pfit.control)
return;
assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -5418,7 +5418,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
return true;
case PIPE_C:
if (!pipe_has_enabled_pch(pipe_B_crtc) ||
- pipe_B_crtc->config.fdi_lanes <= 2) {
+ pipe_B_crtc->config->fdi_lanes <= 2) {
if (pipe_config->fdi_lanes > 2) {
DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
pipe_name(pipe), pipe_config->fdi_lanes);
@@ -5816,7 +5816,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = crtc->pipe;
- enum transcoder transcoder = crtc->config.cpu_transcoder;
+ enum transcoder transcoder = crtc->config->cpu_transcoder;
if (INTEL_INFO(dev)->gen >= 5) {
I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
@@ -5828,7 +5828,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
* registers are not unnecessarily accessed).
*/
if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
- crtc->config.has_drrs) {
+ crtc->config->has_drrs) {
I915_WRITE(PIPE_DATA_M2(transcoder),
TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
@@ -5845,11 +5845,11 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
void intel_dp_set_m_n(struct intel_crtc *crtc)
{
- if (crtc->config.has_pch_encoder)
- intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
+ if (crtc->config->has_pch_encoder)
+ intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
else
- intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
- &crtc->config.dp_m2_n2);
+ intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
+ &crtc->config->dp_m2_n2);
}
static void vlv_update_pll(struct intel_crtc *crtc,
@@ -6217,9 +6217,9 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe = intel_crtc->pipe;
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.base.adjusted_mode;
+ &intel_crtc->config->base.adjusted_mode;
uint32_t crtc_vtotal, crtc_vblank_end;
int vsyncshift = 0;
@@ -6277,8 +6277,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
* always be the user's requested size.
*/
I915_WRITE(PIPESRC(pipe),
- ((intel_crtc->config.pipe_src_w - 1) << 16) |
- (intel_crtc->config.pipe_src_h - 1));
+ ((intel_crtc->config->pipe_src_w - 1) << 16) |
+ (intel_crtc->config->pipe_src_h - 1));
}
static void intel_get_pipe_timings(struct intel_crtc *crtc,
@@ -6354,17 +6354,17 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
(intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
- if (intel_crtc->config.double_wide)
+ if (intel_crtc->config->double_wide)
pipeconf |= PIPECONF_DOUBLE_WIDE;
/* only g4x and later have fancy bpc/dither controls */
if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
/* Bspec claims that we can't use dithering for 30bpp pipes. */
- if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
+ if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
pipeconf |= PIPECONF_DITHER_EN |
PIPECONF_DITHER_TYPE_SP;
- switch (intel_crtc->config.pipe_bpp) {
+ switch (intel_crtc->config->pipe_bpp) {
case 18:
pipeconf |= PIPECONF_6BPC;
break;
@@ -6389,7 +6389,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
}
}
- if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
if (INTEL_INFO(dev)->gen < 4 ||
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
@@ -6398,7 +6398,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
} else
pipeconf |= PIPECONF_PROGRESSIVE;
- if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
+ if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
@@ -7126,7 +7126,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
val = 0;
- switch (intel_crtc->config.pipe_bpp) {
+ switch (intel_crtc->config->pipe_bpp) {
case 18:
val |= PIPECONF_6BPC;
break;
@@ -7144,15 +7144,15 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
BUG();
}
- if (intel_crtc->config.dither)
+ if (intel_crtc->config->dither)
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
- if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
val |= PIPECONF_INTERLACED_ILK;
else
val |= PIPECONF_PROGRESSIVE;
- if (intel_crtc->config.limited_color_range)
+ if (intel_crtc->config->limited_color_range)
val |= PIPECONF_COLOR_RANGE_SELECT;
I915_WRITE(PIPECONF(pipe), val);
@@ -7181,7 +7181,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
* consideration.
*/
- if (intel_crtc->config.limited_color_range)
+ if (intel_crtc->config->limited_color_range)
coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
/*
@@ -7205,7 +7205,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
if (INTEL_INFO(dev)->gen > 6) {
uint16_t postoff = 0;
- if (intel_crtc->config.limited_color_range)
+ if (intel_crtc->config->limited_color_range)
postoff = (16 * (1 << 12) / 255) & 0x1fff;
I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
@@ -7216,7 +7216,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
} else {
uint32_t mode = CSC_MODE_YUV_TO_RGB;
- if (intel_crtc->config.limited_color_range)
+ if (intel_crtc->config->limited_color_range)
mode |= CSC_BLACK_SCREEN_OFFSET;
I915_WRITE(PIPE_CSC_MODE(pipe), mode);
@@ -7229,15 +7229,15 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum pipe pipe = intel_crtc->pipe;
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
uint32_t val;
val = 0;
- if (IS_HASWELL(dev) && intel_crtc->config.dither)
+ if (IS_HASWELL(dev) && intel_crtc->config->dither)
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
- if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
val |= PIPECONF_INTERLACED_ILK;
else
val |= PIPECONF_PROGRESSIVE;
@@ -7251,7 +7251,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
val = 0;
- switch (intel_crtc->config.pipe_bpp) {
+ switch (intel_crtc->config->pipe_bpp) {
case 18:
val |= PIPEMISC_DITHER_6_BPC;
break;
@@ -7269,7 +7269,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
BUG();
}
- if (intel_crtc->config.dither)
+ if (intel_crtc->config->dither)
val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
I915_WRITE(PIPEMISC(pipe), val);
@@ -7530,7 +7530,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
* registers are not unnecessarily read).
*/
if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
- crtc->config.has_drrs) {
+ crtc->config->has_drrs) {
m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
@@ -8282,10 +8282,10 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
if (on)
base = intel_crtc->cursor_addr;
- if (x >= intel_crtc->config.pipe_src_w)
+ if (x >= intel_crtc->config->pipe_src_w)
base = 0;
- if (y >= intel_crtc->config.pipe_src_h)
+ if (y >= intel_crtc->config->pipe_src_h)
base = 0;
if (x < 0) {
@@ -8812,7 +8812,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
struct drm_display_mode *mode;
struct intel_crtc_state pipe_config;
int htot = I915_READ(HTOTAL(cpu_transcoder));
@@ -10769,11 +10769,11 @@ check_crtc_state(struct drm_device *dev)
"(expected %i, found %i)\n", crtc->active, active);
if (active &&
- !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
+ !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
WARN(1, "pipe state doesn't match!\n");
intel_dump_pipe_config(crtc, &pipe_config,
"[hw state]");
- intel_dump_pipe_config(crtc, &crtc->config,
+ intel_dump_pipe_config(crtc, crtc->config,
"[sw state]");
}
}
@@ -10873,7 +10873,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
* one to the value.
*/
if (IS_GEN2(dev)) {
- const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
+ const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
int vtotal;
vtotal = mode->crtc_vtotal;
@@ -10921,6 +10921,13 @@ out:
return pipe_config;
}
+static void intel_crtc_set_state(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
+{
+ kfree(crtc->config);
+ crtc->config = crtc_state;
+}
+
static int __intel_set_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode,
int x, int y, struct drm_framebuffer *fb,
@@ -11000,7 +11007,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
crtc->mode = *mode;
/* mode_set/enable/disable functions rely on a correct pipe
* config. */
- to_intel_crtc(crtc)->config = *pipe_config;
+ intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
/*
* Calculate and store various constants which
@@ -11044,7 +11051,6 @@ done:
if (ret && crtc->enabled)
crtc->mode = *saved_mode;
- kfree(pipe_config);
kfree(saved_mode);
return ret;
}
@@ -11461,7 +11467,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
goto fail;
} else if (pipe_config) {
if (pipe_config->has_audio !=
- to_intel_crtc(set->crtc)->config.has_audio)
+ to_intel_crtc(set->crtc)->config->has_audio)
config->mode_changed = true;
/*
@@ -11886,8 +11892,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
state.clip.x1 = 0;
state.clip.y1 = 0;
- state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
- state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
+ state.clip.x2 = intel_crtc->active ? intel_crtc->config->pipe_src_w : 0;
+ state.clip.y2 = intel_crtc->active ? intel_crtc->config->pipe_src_h : 0;
state.orig_src = state.src;
state.orig_dst = state.dst;
@@ -12169,6 +12175,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state = NULL;
struct drm_plane *primary = NULL;
struct drm_plane *cursor = NULL;
int i, ret;
@@ -12177,6 +12184,11 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
if (intel_crtc == NULL)
return;
+ crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
+ if (!crtc_state)
+ goto fail;
+ intel_crtc_set_state(intel_crtc, crtc_state);
+
primary = intel_primary_plane_create(dev, pipe);
if (!primary)
goto fail;
@@ -12229,6 +12241,7 @@ fail:
drm_plane_cleanup(primary);
if (cursor)
drm_plane_cleanup(cursor);
+ kfree(crtc_state);
kfree(intel_crtc);
}
@@ -13131,7 +13144,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
u32 reg;
/* Clear any frame start delays used for debugging left by the BIOS */
- reg = PIPECONF(crtc->config.cpu_transcoder);
+ reg = PIPECONF(crtc->config->cpu_transcoder);
I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
/* restore vblank interrupts to correct state */
@@ -13335,12 +13348,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
int i;
for_each_intel_crtc(dev, crtc) {
- memset(&crtc->config, 0, sizeof(crtc->config));
+ memset(crtc->config, 0, sizeof(*crtc->config));
- crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
+ crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
crtc->active = dev_priv->display.get_pipe_config(crtc,
- &crtc->config);
+ crtc->config);
crtc->base.enabled = crtc->active;
crtc->primary_enabled = primary_get_hw_state(crtc);
@@ -13377,7 +13390,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (encoder->get_hw_state(encoder, &pipe)) {
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
encoder->base.crtc = &crtc->base;
- encoder->get_config(encoder, &crtc->config);
+ encoder->get_config(encoder, crtc->config);
} else {
encoder->base.crtc = NULL;
}
@@ -13427,7 +13440,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
*/
for_each_intel_crtc(dev, crtc) {
if (crtc->active && i915.fastboot) {
- intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
+ intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
crtc->base.base.id);
drm_mode_debug_printmodeline(&crtc->base.mode);
@@ -13442,7 +13455,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
for_each_pipe(dev_priv, pipe) {
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
intel_sanitize_crtc(crtc);
- intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
+ intel_dump_pipe_config(crtc, crtc->config, "[setup_hw_state]");
}
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 67cdbe8..d6f0d90 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1295,11 +1295,11 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev->dev_private;
u32 dpa_ctl;
- DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
+ DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config->port_clock);
dpa_ctl = I915_READ(DP_A);
dpa_ctl &= ~DP_PLL_FREQ_MASK;
- if (crtc->config.port_clock == 162000) {
+ if (crtc->config->port_clock == 162000) {
/* For a long time we've carried around a ILK-DevA w/a for the
* 160MHz clock. If we're really unlucky, it's still required.
*/
@@ -1324,7 +1324,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = dp_to_dig_port(intel_dp)->port;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
/*
* There are four kinds of DP registers:
@@ -1352,7 +1352,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
- if (crtc->config.has_audio)
+ if (crtc->config->has_audio)
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
/* Split out the IBX/CPU vs CPT settings */
@@ -2102,7 +2102,7 @@ static void intel_disable_dp(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- if (crtc->config.has_audio)
+ if (crtc->config->has_audio)
intel_audio_codec_disable(encoder);
if (HAS_PSR(dev) && !HAS_DDI(dev))
@@ -2312,7 +2312,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
intel_dp_complete_link_train(intel_dp);
intel_dp_stop_link_train(intel_dp);
- if (crtc->config.has_audio) {
+ if (crtc->config->has_audio) {
DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
pipe_name(crtc->pipe));
intel_audio_codec_enable(encoder);
@@ -4780,7 +4780,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
return;
}
- config = &intel_crtc->config;
+ config = intel_crtc->config;
if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
@@ -4802,7 +4802,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
}
if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
- reg = PIPECONF(intel_crtc->config.cpu_transcoder);
+ reg = PIPECONF(intel_crtc->config->cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
val |= PIPECONF_EDP_RR_MODE_SWITCH;
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 257aca1..28b6ee4 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -157,7 +157,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
if (intel_dp->active_mst_links == 0) {
enum port port = intel_ddi_get_encoder_port(encoder);
- I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config.ddi_pll_sel);
+ I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config->ddi_pll_sel);
intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
@@ -170,7 +170,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
}
ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr,
- intel_mst->port, intel_crtc->config.pbn, &slots);
+ intel_mst->port, intel_crtc->config->pbn,
+ &slots);
if (ret == false) {
DRM_ERROR("failed to allocate vcpi\n");
return;
@@ -223,7 +224,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
+ enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
u32 temp, flags = 0;
pipe_config->has_dp_encoder = true;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 175b853..01d6fa1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -439,7 +439,7 @@ struct intel_crtc {
uint32_t cursor_base;
struct intel_plane_config plane_config;
- struct intel_crtc_state config;
+ struct intel_crtc_state *config;
bool new_enabled;
/* reset counter value when the last flip was submitted */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 25291e9..5d9ec7b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -232,7 +232,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
I915_WRITE(DPLL(pipe), tmp);
/* update the hw state for DPLL */
- intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
+ intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
DPLL_REFA_CLK_ENABLE_VLV;
tmp = I915_READ(DSPCLK_GATE_D);
@@ -494,7 +494,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
- unsigned int bpp = intel_crtc->config.pipe_bpp;
+ unsigned int bpp = intel_crtc->config->pipe_bpp;
unsigned int lane_count = intel_dsi->lane_count;
u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
@@ -549,9 +549,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.base.adjusted_mode;
+ &intel_crtc->config->base.adjusted_mode;
enum port port;
- unsigned int bpp = intel_crtc->config.pipe_bpp;
+ unsigned int bpp = intel_crtc->config->pipe_bpp;
u32 val, tmp;
u16 mode_hdisplay;
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 108f058..706ab99 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -186,8 +186,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
u32 temp = I915_READ(dvo_reg);
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
- &crtc->config.base.mode,
- &crtc->config.base.adjusted_mode);
+ &crtc->config->base.mode,
+ &crtc->config->base.adjusted_mode);
I915_WRITE(dvo_reg, temp | DVO_ENABLE);
I915_READ(dvo_reg);
@@ -221,7 +221,7 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
/* We call connector dpms manually below in case pipe dpms doesn't
* change due to cloning. */
if (mode == DRM_MODE_DPMS_ON) {
- config = &to_intel_crtc(crtc)->config;
+ config = to_intel_crtc(crtc)->config;
intel_dvo->base.connectors_active = true;
@@ -295,7 +295,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
int pipe = crtc->pipe;
u32 dvo_val;
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 1a9a727..f426e7c 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -431,7 +431,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
DRM_DEBUG_KMS("looking for current mode on connector %s\n",
connector->name);
intel_mode_from_pipe_config(&encoder->crtc->hwmode,
- &to_intel_crtc(encoder->crtc)->config);
+ to_intel_crtc(encoder->crtc)->config);
modes[i] = &encoder->crtc->hwmode;
}
crtcs[i] = new_crtc;
@@ -563,7 +563,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
* pipe. Note we need to use the selected fb's pitch and bpp
* rather than the current pipe's, since they differ.
*/
- cur_size = intel_crtc->config.base.adjusted_mode.crtc_hdisplay;
+ cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay;
cur_size = cur_size * fb->base.bits_per_pixel / 8;
if (fb->base.pitches[0] < cur_size) {
DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n",
@@ -574,13 +574,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
break;
}
- cur_size = intel_crtc->config.base.adjusted_mode.crtc_vdisplay;
+ cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1);
cur_size *= fb->base.pitches[0];
DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
pipe_name(intel_crtc->pipe),
- intel_crtc->config.base.adjusted_mode.crtc_hdisplay,
- intel_crtc->config.base.adjusted_mode.crtc_vdisplay,
+ intel_crtc->config->base.adjusted_mode.crtc_hdisplay,
+ intel_crtc->config->base.adjusted_mode.crtc_vdisplay,
fb->base.bits_per_pixel,
cur_size);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 02ff3e2..200a0e7 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -337,13 +337,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
- u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
+ u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
u32 data_reg;
int i;
u32 val = I915_READ(ctl_reg);
data_reg = hsw_infoframe_data_reg(type,
- intel_crtc->config.cpu_transcoder,
+ intel_crtc->config->cpu_transcoder,
dev_priv);
if (data_reg == 0)
return;
@@ -371,7 +371,7 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
- u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
+ u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
u32 val = I915_READ(ctl_reg);
return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
@@ -436,7 +436,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
}
if (intel_hdmi->rgb_quant_range_selectable) {
- if (intel_crtc->config.limited_color_range)
+ if (intel_crtc->config->limited_color_range)
frame.avi.quantization_range =
HDMI_QUANTIZATION_RANGE_LIMITED;
else
@@ -672,7 +672,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
- u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
+ u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
u32 val = I915_READ(reg);
assert_hdmi_port_disabled(intel_hdmi);
@@ -700,7 +700,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
- struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
u32 hdmi_val;
hdmi_val = SDVO_ENCODING_HDMI;
@@ -711,12 +711,12 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
- if (crtc->config.pipe_bpp > 24)
+ if (crtc->config->pipe_bpp > 24)
hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
else
hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
- if (crtc->config.has_hdmi_sink)
+ if (crtc->config->has_hdmi_sink)
hdmi_val |= HDMI_MODE_SELECT_HDMI;
if (HAS_PCH_CPT(dev))
@@ -814,7 +814,7 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
u32 temp;
u32 enable_bits = SDVO_ENABLE;
- if (intel_crtc->config.has_audio)
+ if (intel_crtc->config->has_audio)
enable_bits |= SDVO_AUDIO_ENABLE;
temp = I915_READ(intel_hdmi->hdmi_reg);
@@ -845,8 +845,8 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
POSTING_READ(intel_hdmi->hdmi_reg);
}
- if (intel_crtc->config.has_audio) {
- WARN_ON(!intel_crtc->config.has_hdmi_sink);
+ if (intel_crtc->config->has_audio) {
+ WARN_ON(!intel_crtc->config->has_hdmi_sink);
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
pipe_name(intel_crtc->pipe));
intel_audio_codec_enable(encoder);
@@ -866,7 +866,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
u32 temp;
u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
- if (crtc->config.has_audio)
+ if (crtc->config->has_audio)
intel_audio_codec_disable(encoder);
temp = I915_READ(intel_hdmi->hdmi_reg);
@@ -1252,12 +1252,12 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.base.adjusted_mode;
+ &intel_crtc->config->base.adjusted_mode;
intel_hdmi_prepare(encoder);
intel_hdmi->set_infoframes(&encoder->base,
- intel_crtc->config.has_hdmi_sink,
+ intel_crtc->config->has_hdmi_sink,
adjusted_mode);
}
@@ -1270,7 +1270,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.base.adjusted_mode;
+ &intel_crtc->config->base.adjusted_mode;
enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe;
u32 val;
@@ -1302,7 +1302,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->dpio_lock);
intel_hdmi->set_infoframes(&encoder->base,
- intel_crtc->config.has_hdmi_sink,
+ intel_crtc->config->has_hdmi_sink,
adjusted_mode);
intel_enable_hdmi(encoder);
@@ -1467,7 +1467,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.base.adjusted_mode;
+ &intel_crtc->config->base.adjusted_mode;
enum dpio_channel ch = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe;
int data, i;
@@ -1593,7 +1593,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->dpio_lock);
intel_hdmi->set_infoframes(&encoder->base,
- intel_crtc->config.has_hdmi_sink,
+ intel_crtc->config->has_hdmi_sink,
adjusted_mode);
intel_enable_hdmi(encoder);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 9d174cf..c7c6414 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -139,7 +139,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
const struct drm_display_mode *adjusted_mode =
- &crtc->config.base.adjusted_mode;
+ &crtc->config->base.adjusted_mode;
int pipe = crtc->pipe;
u32 temp;
@@ -167,7 +167,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
/* set the corresponsding LVDS_BORDER bit */
temp &= ~LVDS_BORDER_ENABLE;
- temp |= crtc->config.gmch_pfit.lvds_border_bits;
+ temp |= crtc->config->gmch_pfit.lvds_border_bits;
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
*/
@@ -190,7 +190,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
if (INTEL_INFO(dev)->gen == 4) {
/* Bspec wording suggests that LVDS port dithering only exists
* for 18bpp panels. */
- if (crtc->config.dither && crtc->config.pipe_bpp == 18)
+ if (crtc->config->dither && crtc->config->pipe_bpp == 18)
temp |= LVDS_ENABLE_DITHER;
else
temp &= ~LVDS_ENABLE_DITHER;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 973c9de..f93dfc1 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -856,7 +856,7 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
return -EINVAL;
/* can't use the overlay with double wide pipe */
- if (crtc->config.double_wide)
+ if (crtc->config->double_wide)
return -EINVAL;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 47b23b7..22e49f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -574,7 +574,7 @@ void intel_update_fbc(struct drm_device *dev)
intel_crtc = to_intel_crtc(crtc);
fb = crtc->primary->fb;
obj = intel_fb_obj(fb);
- adjusted_mode = &intel_crtc->config.base.adjusted_mode;
+ adjusted_mode = &intel_crtc->config->base.adjusted_mode;
if (i915.enable_fbc < 0) {
if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
@@ -604,8 +604,8 @@ void intel_update_fbc(struct drm_device *dev)
max_width = 2048;
max_height = 1536;
}
- if (intel_crtc->config.pipe_src_w > max_width ||
- intel_crtc->config.pipe_src_h > max_height) {
+ if (intel_crtc->config->pipe_src_w > max_width ||
+ intel_crtc->config->pipe_src_h > max_height) {
if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
DRM_DEBUG_KMS("mode too large for compression, disabling\n");
goto out_disable;
@@ -1157,7 +1157,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
int clock;
- adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
clock = adjusted_mode->crtc_clock;
/* Display SR */
@@ -1226,10 +1226,10 @@ static bool g4x_compute_wm0(struct drm_device *dev,
return false;
}
- adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
- hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
+ hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
pixel_size = crtc->primary->fb->bits_per_pixel / 8;
/* Use the small buffer method to calculate plane watermark */
@@ -1313,10 +1313,10 @@ static bool g4x_compute_srwm(struct drm_device *dev,
}
crtc = intel_get_crtc_for_plane(dev, plane);
- adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
- hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
+ hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
pixel_size = crtc->primary->fb->bits_per_pixel / 8;
line_time_us = max(htotal * 1000 / clock, 1);
@@ -1347,7 +1347,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
int entries;
- int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
+ int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
if (WARN(clock == 0, "Pixel clock is zero!\n"))
return false;
@@ -1677,10 +1677,10 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
/* self-refresh has much higher latency */
static const int sr_latency_ns = 12000;
const struct drm_display_mode *adjusted_mode =
- &to_intel_crtc(crtc)->config.base.adjusted_mode;
+ &to_intel_crtc(crtc)->config->base.adjusted_mode;
int clock = adjusted_mode->crtc_clock;
int htotal = adjusted_mode->crtc_htotal;
- int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
+ int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
unsigned long line_time_us;
int entries;
@@ -1762,7 +1762,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (IS_GEN2(dev))
cpp = 4;
- adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
@@ -1784,7 +1784,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (IS_GEN2(dev))
cpp = 4;
- adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
@@ -1823,10 +1823,10 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
const struct drm_display_mode *adjusted_mode =
- &to_intel_crtc(enabled)->config.base.adjusted_mode;
+ &to_intel_crtc(enabled)->config->base.adjusted_mode;
int clock = adjusted_mode->crtc_clock;
int htotal = adjusted_mode->crtc_htotal;
- int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
+ int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
unsigned long line_time_us;
int entries;
@@ -1879,7 +1879,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
if (crtc == NULL)
return;
- adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
+ adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
&i845_wm_info,
dev_priv->display.get_fifo_size(dev, 0),
@@ -1898,17 +1898,17 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pixel_rate;
- pixel_rate = intel_crtc->config.base.adjusted_mode.crtc_clock;
+ pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
* adjust the pixel_rate here. */
- if (intel_crtc->config.pch_pfit.enabled) {
+ if (intel_crtc->config->pch_pfit.enabled) {
uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
- uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
+ uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
- pipe_w = intel_crtc->config.pipe_src_w;
- pipe_h = intel_crtc->config.pipe_src_h;
+ pipe_w = intel_crtc->config->pipe_src_w;
+ pipe_h = intel_crtc->config->pipe_src_h;
pfit_w = (pfit_size >> 16) & 0xFFFF;
pfit_h = pfit_size & 0xFFFF;
if (pipe_w < pfit_w)
@@ -2261,7 +2261,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
+ struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
u32 linetime, ips_linetime;
if (!intel_crtc_active(crtc))
@@ -2521,11 +2521,11 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
return;
p->active = true;
- p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
+ p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
p->cur.bytes_per_pixel = 4;
- p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
+ p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
p->cur.horiz_pixels = intel_crtc->cursor_width;
/* TODO: for now, assume primary and cursor planes are always enabled. */
p->pri.enabled = true;
@@ -3265,8 +3265,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
p->active = intel_crtc_active(crtc);
if (p->active) {
- p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
- p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
+ p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
+ p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
/*
* For now, assume primary and cursor planes are always enabled.
@@ -3274,8 +3274,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
p->plane[0].enabled = true;
p->plane[0].bytes_per_pixel =
crtc->primary->fb->bits_per_pixel / 8;
- p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w;
- p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h;
+ p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
+ p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
p->cursor.enabled = true;
p->cursor.bytes_per_pixel = 4;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b8713e4..494b132 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -79,8 +79,8 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
- u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
- u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
+ u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
+ u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
uint32_t *data = (uint32_t *) vsc_psr;
unsigned int i;
@@ -274,13 +274,13 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
if (IS_BROADWELL(dev))
goto out;
- if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
+ if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
S3D_ENABLE) {
DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
return false;
}
- if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
return false;
}
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index e4d5da5..8c8d807 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1007,7 +1007,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
}
if (intel_sdvo->rgb_quant_range_selectable) {
- if (intel_crtc->config.limited_color_range)
+ if (intel_crtc->config->limited_color_range)
frame.avi.quantization_range =
HDMI_QUANTIZATION_RANGE_LIMITED;
else
@@ -1181,8 +1181,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
- &crtc->config.base.adjusted_mode;
- struct drm_display_mode *mode = &crtc->config.base.mode;
+ &crtc->config->base.adjusted_mode;
+ struct drm_display_mode *mode = &crtc->config->base.mode;
struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
u32 sdvox;
struct intel_sdvo_in_out_map in_out;
@@ -1224,7 +1224,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
if (!intel_sdvo_set_target_input(intel_sdvo))
return;
- if (crtc->config.has_hdmi_sink) {
+ if (crtc->config->has_hdmi_sink) {
intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
intel_sdvo_set_colorimetry(intel_sdvo,
SDVO_COLORIMETRY_RGB256);
@@ -1244,7 +1244,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
DRM_INFO("Setting input timings on %s failed\n",
SDVO_NAME(intel_sdvo));
- switch (crtc->config.pixel_multiplier) {
+ switch (crtc->config->pixel_multiplier) {
default:
WARN(1, "unknown pixel mutlipler specified\n");
case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
@@ -1259,7 +1259,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
/* The real mode polarity is set by the SDVO commands, using
* struct intel_sdvo_dtd. */
sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
- if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range)
+ if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
sdvox |= HDMI_COLOR_RANGE_16_235;
if (INTEL_INFO(dev)->gen < 5)
sdvox |= SDVO_BORDER_ENABLE;
@@ -1289,7 +1289,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
/* done in crtc_mode_set as it lives inside the dpll register */
} else {
- sdvox |= (crtc->config.pixel_multiplier - 1)
+ sdvox |= (crtc->config->pixel_multiplier - 1)
<< SDVO_PORT_MULTIPLY_SHIFT;
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 454b25d..937bd72 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -79,7 +79,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
{
struct drm_device *dev = crtc->base.dev;
- const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
+ const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
enum pipe pipe = crtc->pipe;
long timeout = msecs_to_jiffies_timeout(1);
int scanline, min, max, vblank_start;
--
1.9.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 7/8] drm/i915: Make intel_crtc->config a pointer
2014-12-11 12:38 ` [PATCH 7/8] drm/i915: Make intel_crtc->config a pointer Ander Conselvan de Oliveira
@ 2014-12-15 19:30 ` Matt Roper
0 siblings, 0 replies; 20+ messages in thread
From: Matt Roper @ 2014-12-15 19:30 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx, shuang.he
On Thu, Dec 11, 2014 at 02:38:10PM +0200, Ander Conselvan de Oliveira wrote:
> To match the semantics of drm_crtc->state, which this will eventually
> become.
>
> @@ struct intel_crtc *crtc; @@
> -&crtc->config
> +crtc->config
> @@ struct intel_crtc *crtc; identifier member; @@
> -crtc->config.member
> +crtc->config->member
> @@ struct drm_crtc *crtc; @@
> -&to_intel_crtc(crtc)->config
> +to_intel_crtc(crtc)->config
> @@ struct drm_crtc *crtc; identifier member; @@
> -to_intel_crtc(crtc)->config.member
> +to_intel_crtc(crtc)->config->member
Just to avoid confusion, you may want to indicate that there are a few
changes beyond the coccinelle spatch listed here (allocation in
intel_crtc_init, assignment with new intel_crtc_set_state, etc.).
Also, I may be missing it happening somewhere else in the large patch,
but do we need an intel_crtc_set_state(intel_crtc, NULL) in
intel_crtc_destroy() to ensure that our final state doesn't leak when we
rmmod?
Matt
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 +-
> drivers/gpu/drm/i915/i915_irq.c | 8 +-
> drivers/gpu/drm/i915/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 52 +++----
> drivers/gpu/drm/i915/intel_display.c | 275 ++++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_dp.c | 16 +-
> drivers/gpu/drm/i915/intel_dp_mst.c | 7 +-
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_dsi.c | 8 +-
> drivers/gpu/drm/i915/intel_dvo.c | 8 +-
> drivers/gpu/drm/i915/intel_fbdev.c | 10 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 36 ++---
> drivers/gpu/drm/i915/intel_lvds.c | 6 +-
> drivers/gpu/drm/i915/intel_overlay.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 56 +++----
> drivers/gpu/drm/i915/intel_psr.c | 8 +-
> drivers/gpu/drm/i915/intel_sdvo.c | 14 +-
> drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> 19 files changed, 270 insertions(+), 256 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index d0e445e..a724e8c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2572,7 +2572,7 @@ static int i915_display_info(struct seq_file *m, void *unused)
>
> seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
> crtc->base.base.id, pipe_name(crtc->pipe),
> - yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
> + yesno(crtc->active), crtc->config->pipe_src_w, crtc->config->pipe_src_h);
> if (crtc->active) {
> intel_crtc_info(m, crtc);
>
> @@ -3280,9 +3280,9 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
> * relevant on hsw with pipe A when using the always-on power well
> * routing.
> */
> - if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
> - !crtc->config.pch_pfit.enabled) {
> - crtc->config.pch_pfit.force_thru = true;
> + if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
> + !crtc->config->pch_pfit.enabled) {
> + crtc->config->pch_pfit.force_thru = true;
>
> intel_display_power_get(dev_priv,
> POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
> @@ -3306,8 +3306,8 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
> * relevant on hsw with pipe A when using the always-on power well
> * routing.
> */
> - if (crtc->config.pch_pfit.force_thru) {
> - crtc->config.pch_pfit.force_thru = false;
> + if (crtc->config->pch_pfit.force_thru) {
> + crtc->config->pch_pfit.force_thru = false;
>
> dev_priv->display.crtc_disable(&crtc->base);
> dev_priv->display.crtc_enable(&crtc->base);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 11e209e..e55b275 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -567,7 +567,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
> struct intel_crtc *intel_crtc =
> to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> const struct drm_display_mode *mode =
> - &intel_crtc->config.base.adjusted_mode;
> + &intel_crtc->config->base.adjusted_mode;
>
> htotal = mode->crtc_htotal;
> hsync_start = mode->crtc_hsync_start;
> @@ -638,7 +638,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
> + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
> enum pipe pipe = crtc->pipe;
> int position, vtotal;
>
> @@ -665,7 +665,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - const struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
> + const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
> int position;
> int vbl_start, vbl_end, hsync_start, htotal, vtotal;
> bool in_vbl = true;
> @@ -823,7 +823,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
> return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
> vblank_time, flags,
> crtc,
> - &to_intel_crtc(crtc)->config.base.adjusted_mode);
> + &to_intel_crtc(crtc)->config->base.adjusted_mode);
> }
>
> static bool intel_hpd_irq_event(struct drm_device *dev,
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index fe8c496..e84a798 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -397,7 +397,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
> {
> struct drm_encoder *encoder = &intel_encoder->base;
> struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
> - struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
> + struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
> struct drm_connector *connector;
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index e4f6d49..bb55368 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -157,7 +157,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
> u32 adpa;
>
> if (INTEL_INFO(dev)->gen >= 5)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 970ca30..c409ccc 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -328,7 +328,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> /* Enable the PCH Receiver FDI PLL */
> rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
> FDI_RX_PLL_ENABLE |
> - FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> + FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> POSTING_READ(_FDI_RXA_CTL);
> udelay(220);
> @@ -338,8 +338,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>
> /* Configure Port Clock Select */
> - I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
> - WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
> + I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
> + WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
>
> /* Start the training iterating through available voltages and emphasis,
> * testing each value twice. */
> @@ -357,7 +357,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> * port reversal bit */
> I915_WRITE(DDI_BUF_CTL(PORT_E),
> DDI_BUF_CTL_ENABLE |
> - ((intel_crtc->config.fdi_lanes - 1) << 1) |
> + ((intel_crtc->config->fdi_lanes - 1) << 1) |
> DDI_BUF_TRANS_SELECT(i / 2));
> POSTING_READ(DDI_BUF_CTL(PORT_E));
>
> @@ -1186,13 +1186,13 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> int type = intel_encoder->type;
> uint32_t temp;
>
> if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
> temp = TRANS_MSA_SYNC_CLK;
> - switch (intel_crtc->config.pipe_bpp) {
> + switch (intel_crtc->config->pipe_bpp) {
> case 18:
> temp |= TRANS_MSA_6_BPC;
> break;
> @@ -1217,7 +1217,7 @@ void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> uint32_t temp;
> temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (state == true)
> @@ -1235,7 +1235,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum pipe pipe = intel_crtc->pipe;
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> int type = intel_encoder->type;
> uint32_t temp;
> @@ -1244,7 +1244,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> temp = TRANS_DDI_FUNC_ENABLE;
> temp |= TRANS_DDI_SELECT_PORT(port);
>
> - switch (intel_crtc->config.pipe_bpp) {
> + switch (intel_crtc->config->pipe_bpp) {
> case 18:
> temp |= TRANS_DDI_BPC_6;
> break;
> @@ -1261,9 +1261,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> BUG();
> }
>
> - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> temp |= TRANS_DDI_PVSYNC;
> - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> temp |= TRANS_DDI_PHSYNC;
>
> if (cpu_transcoder == TRANSCODER_EDP) {
> @@ -1274,8 +1274,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> * using motion blur mitigation (which we don't
> * support). */
> if (IS_HASWELL(dev) &&
> - (intel_crtc->config.pch_pfit.enabled ||
> - intel_crtc->config.pch_pfit.force_thru))
> + (intel_crtc->config->pch_pfit.enabled ||
> + intel_crtc->config->pch_pfit.force_thru))
> temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
> else
> temp |= TRANS_DDI_EDP_INPUT_A_ON;
> @@ -1293,14 +1293,14 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> }
>
> if (type == INTEL_OUTPUT_HDMI) {
> - if (intel_crtc->config.has_hdmi_sink)
> + if (intel_crtc->config->has_hdmi_sink)
> temp |= TRANS_DDI_MODE_SELECT_HDMI;
> else
> temp |= TRANS_DDI_MODE_SELECT_DVI;
>
> } else if (type == INTEL_OUTPUT_ANALOG) {
> temp |= TRANS_DDI_MODE_SELECT_FDI;
> - temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
> + temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
>
> } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
> type == INTEL_OUTPUT_EDP) {
> @@ -1450,7 +1450,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>
> if (cpu_transcoder != TRANSCODER_EDP)
> I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> @@ -1460,7 +1460,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
> void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
> {
> struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>
> if (cpu_transcoder != TRANSCODER_EDP)
> I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> @@ -1482,7 +1482,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
> }
>
> if (IS_SKYLAKE(dev)) {
> - uint32_t dpll = crtc->config.ddi_pll_sel;
> + uint32_t dpll = crtc->config->ddi_pll_sel;
> uint32_t val;
>
> /*
> @@ -1497,7 +1497,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
> val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
> DPLL_CTRL1_SSC(dpll) |
> DPLL_CRTL1_LINK_RATE_MASK(dpll));
> - val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6);
> + val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
>
> I915_WRITE(DPLL_CTRL1, val);
> POSTING_READ(DPLL_CTRL1);
> @@ -1514,8 +1514,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
> I915_WRITE(DPLL_CTRL2, val);
>
> } else {
> - WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
> - I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
> + WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
> + I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
> }
>
> if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
> @@ -1532,8 +1532,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>
> intel_hdmi->set_infoframes(encoder,
> - crtc->config.has_hdmi_sink,
> - &crtc->config.base.adjusted_mode);
> + crtc->config->has_hdmi_sink,
> + &crtc->config->base.adjusted_mode);
> }
> }
>
> @@ -1607,7 +1607,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
> intel_psr_enable(intel_dp);
> }
>
> - if (intel_crtc->config.has_audio) {
> + if (intel_crtc->config->has_audio) {
> intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
> intel_audio_codec_enable(intel_encoder);
> }
> @@ -1622,7 +1622,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (intel_crtc->config.has_audio) {
> + if (intel_crtc->config->has_audio) {
> intel_audio_codec_disable(intel_encoder);
> intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
> }
> @@ -2031,7 +2031,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> struct intel_hdmi *intel_hdmi;
> u32 temp, flags = 0;
> struct drm_device *dev = dev_priv->dev;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a032a1d..462f22a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -895,7 +895,7 @@ bool intel_crtc_active(struct drm_crtc *crtc)
> * properly reconstruct framebuffers.
> */
> return intel_crtc->active && crtc->primary->fb &&
> - intel_crtc->config.base.adjusted_mode.crtc_clock;
> + intel_crtc->config->base.adjusted_mode.crtc_clock;
> }
>
> enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> @@ -904,7 +904,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>
> - return intel_crtc->config.cpu_transcoder;
> + return intel_crtc->config->cpu_transcoder;
> }
>
> static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
> @@ -946,7 +946,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
>
> if (INTEL_INFO(dev)->gen >= 4) {
> @@ -1052,10 +1052,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
>
> - if (crtc->config.shared_dpll < 0)
> + if (crtc->config->shared_dpll < 0)
> return NULL;
>
> - return &dev_priv->shared_dplls[crtc->config.shared_dpll];
> + return &dev_priv->shared_dplls[crtc->config->shared_dpll];
> }
>
> /* For ILK+ */
> @@ -1599,7 +1599,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> int reg = DPLL(crtc->pipe);
> - u32 dpll = crtc->config.dpll_hw_state.dpll;
> + u32 dpll = crtc->config->dpll_hw_state.dpll;
>
> assert_pipe_disabled(dev_priv, crtc->pipe);
>
> @@ -1629,7 +1629,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>
> if (INTEL_INFO(dev)->gen >= 4) {
> I915_WRITE(DPLL_MD(crtc->pipe),
> - crtc->config.dpll_hw_state.dpll_md);
> + crtc->config->dpll_hw_state.dpll_md);
> } else {
> /* The pixel multiplier can only be updated once the
> * DPLL is enabled and the clocks are stable.
> @@ -2034,7 +2034,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
> else
> assert_pll_enabled(dev_priv, pipe);
> else {
> - if (crtc->config.has_pch_encoder) {
> + if (crtc->config->has_pch_encoder) {
> /* if driving the PCH, we need FDI enabled */
> assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
> assert_fdi_tx_pll_enabled(dev_priv,
> @@ -2068,7 +2068,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
> static void intel_disable_pipe(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
> - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
> int reg;
> u32 val;
> @@ -2090,7 +2090,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
> * Double wide has implications for planes
> * so best keep it disabled when not needed.
> */
> - if (crtc->config.double_wide)
> + if (crtc->config->double_wide)
> val &= ~PIPECONF_DOUBLE_WIDE;
>
> /* Don't disable pipe or pipe PLLs if needed */
> @@ -2468,13 +2468,13 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> * which should always be the user's requested size.
> */
> I915_WRITE(DSPSIZE(plane),
> - ((intel_crtc->config.pipe_src_h - 1) << 16) |
> - (intel_crtc->config.pipe_src_w - 1));
> + ((intel_crtc->config->pipe_src_h - 1) << 16) |
> + (intel_crtc->config->pipe_src_w - 1));
> I915_WRITE(DSPPOS(plane), 0);
> } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> I915_WRITE(PRIMSIZE(plane),
> - ((intel_crtc->config.pipe_src_h - 1) << 16) |
> - (intel_crtc->config.pipe_src_w - 1));
> + ((intel_crtc->config->pipe_src_h - 1) << 16) |
> + (intel_crtc->config->pipe_src_w - 1));
> I915_WRITE(PRIMPOS(plane), 0);
> I915_WRITE(PRIMCNSTALPHA(plane), 0);
> }
> @@ -2532,14 +2532,14 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
> dspcntr |= DISPPLANE_ROTATE_180;
>
> - x += (intel_crtc->config.pipe_src_w - 1);
> - y += (intel_crtc->config.pipe_src_h - 1);
> + x += (intel_crtc->config->pipe_src_w - 1);
> + y += (intel_crtc->config->pipe_src_h - 1);
>
> /* Finding the last pixel of the last line of the display
> data and adding to linear_offset*/
> linear_offset +=
> - (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
> - (intel_crtc->config.pipe_src_w - 1) * pixel_size;
> + (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> + (intel_crtc->config->pipe_src_w - 1) * pixel_size;
> }
>
> I915_WRITE(reg, dspcntr);
> @@ -2635,14 +2635,14 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> dspcntr |= DISPPLANE_ROTATE_180;
>
> if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> - x += (intel_crtc->config.pipe_src_w - 1);
> - y += (intel_crtc->config.pipe_src_h - 1);
> + x += (intel_crtc->config->pipe_src_w - 1);
> + y += (intel_crtc->config->pipe_src_h - 1);
>
> /* Finding the last pixel of the last line of the display
> data and adding to linear_offset*/
> linear_offset +=
> - (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
> - (intel_crtc->config.pipe_src_w - 1) * pixel_size;
> + (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
> + (intel_crtc->config->pipe_src_w - 1) * pixel_size;
> }
> }
>
> @@ -2741,8 +2741,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> I915_WRITE(PLANE_POS(pipe, 0), 0);
> I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
> I915_WRITE(PLANE_SIZE(pipe, 0),
> - (intel_crtc->config.pipe_src_h - 1) << 16 |
> - (intel_crtc->config.pipe_src_w - 1));
> + (intel_crtc->config->pipe_src_h - 1) << 16 |
> + (intel_crtc->config->pipe_src_w - 1));
> I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
>
> @@ -2938,20 +2938,20 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
> * then update the pipesrc and pfit state, even on the flip path.
> */
>
> - adjusted_mode = &crtc->config.base.adjusted_mode;
> + adjusted_mode = &crtc->config->base.adjusted_mode;
>
> I915_WRITE(PIPESRC(crtc->pipe),
> ((adjusted_mode->crtc_hdisplay - 1) << 16) |
> (adjusted_mode->crtc_vdisplay - 1));
> - if (!crtc->config.pch_pfit.enabled &&
> + if (!crtc->config->pch_pfit.enabled &&
> (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
> intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
> I915_WRITE(PF_CTL(crtc->pipe), 0);
> I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
> I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
> }
> - crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
> - crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
> + crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
> + crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
> }
>
> static void intel_fdi_normal_train(struct drm_crtc *crtc)
> @@ -2998,7 +2998,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
> static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
> {
> return crtc->base.enabled && crtc->active &&
> - crtc->config.has_pch_encoder;
> + crtc->config->has_pch_encoder;
> }
>
> static void ivb_modeset_global_resources(struct drm_device *dev)
> @@ -3053,7 +3053,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
> reg = FDI_TX_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~FDI_DP_PORT_WIDTH_MASK;
> - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> temp &= ~FDI_LINK_TRAIN_NONE;
> temp |= FDI_LINK_TRAIN_PATTERN_1;
> I915_WRITE(reg, temp | FDI_TX_ENABLE);
> @@ -3151,7 +3151,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
> reg = FDI_TX_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~FDI_DP_PORT_WIDTH_MASK;
> - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> temp &= ~FDI_LINK_TRAIN_NONE;
> temp |= FDI_LINK_TRAIN_PATTERN_1;
> temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> @@ -3302,7 +3302,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
> reg = FDI_TX_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~FDI_DP_PORT_WIDTH_MASK;
> - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
> temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> temp |= snb_b_fdi_train_param[j/2];
> @@ -3390,7 +3390,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
> - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> + temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
> I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
>
> @@ -3574,7 +3574,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
> + int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
> u32 divsel, phaseinc, auxdiv, phasedir = 0;
> u32 temp;
>
> @@ -3663,7 +3663,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
>
> I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
> I915_READ(HTOTAL(cpu_transcoder)));
> @@ -3709,7 +3709,7 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
> case PIPE_A:
> break;
> case PIPE_B:
> - if (intel_crtc->config.fdi_lanes > 2)
> + if (intel_crtc->config->fdi_lanes > 2)
> WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
> else
> cpt_enable_fdi_bc_bifurcation(dev);
> @@ -3761,7 +3761,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> temp = I915_READ(PCH_DPLL_SEL);
> temp |= TRANS_DPLL_ENABLE(pipe);
> sel = TRANS_DPLLB_SEL(pipe);
> - if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
> + if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
> temp |= sel;
> else
> temp &= ~sel;
> @@ -3784,7 +3784,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> intel_fdi_normal_train(crtc);
>
> /* For PCH DP, enable TRANS_DP_CTL */
> - if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
> + if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
> u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> reg = TRANS_DP_CTL(pipe);
> temp = I915_READ(reg);
> @@ -3825,7 +3825,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>
> assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
>
> @@ -3855,7 +3855,7 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
> WARN_ON(pll->active);
> }
>
> - crtc->config.shared_dpll = DPLL_ID_PRIVATE;
> + crtc->config->shared_dpll = DPLL_ID_PRIVATE;
> }
>
> struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
> @@ -4009,10 +4009,10 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe = crtc->pipe;
>
> - if (crtc->config.pch_pfit.enabled) {
> + if (crtc->config->pch_pfit.enabled) {
> I915_WRITE(PS_CTL(pipe), PS_ENABLE);
> - I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
> - I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
> + I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
> + I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
> }
> }
>
> @@ -4022,7 +4022,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe = crtc->pipe;
>
> - if (crtc->config.pch_pfit.enabled) {
> + if (crtc->config->pch_pfit.enabled) {
> /* Force use of hard-coded filter coefficients
> * as some pre-programmed values are broken,
> * e.g. x201.
> @@ -4032,8 +4032,8 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
> PF_PIPE_SEL_IVB(pipe));
> else
> I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
> - I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
> - I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
> + I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
> + I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
> }
> }
>
> @@ -4070,7 +4070,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (!crtc->config.ips_enabled)
> + if (!crtc->config->ips_enabled)
> return;
>
> /* We can only enable IPS after we enable a plane and wait for a vblank */
> @@ -4103,7 +4103,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (!crtc->config.ips_enabled)
> + if (!crtc->config->ips_enabled)
> return;
>
> assert_plane_enabled(dev_priv, crtc->plane);
> @@ -4152,7 +4152,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
> /* Workaround : Do not read or write the pipe palette/gamma data while
> * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> */
> - if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
> + if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
> ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
> GAMMA_MODE_MODE_SPLIT)) {
> hsw_disable_ips(intel_crtc);
> @@ -4254,17 +4254,17 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->active)
> return;
>
> - if (intel_crtc->config.has_pch_encoder)
> + if (intel_crtc->config->has_pch_encoder)
> intel_prepare_shared_dpll(intel_crtc);
>
> - if (intel_crtc->config.has_dp_encoder)
> + if (intel_crtc->config->has_dp_encoder)
> intel_dp_set_m_n(intel_crtc);
>
> intel_set_pipe_timings(intel_crtc);
>
> - if (intel_crtc->config.has_pch_encoder) {
> + if (intel_crtc->config->has_pch_encoder) {
> intel_cpu_transcoder_set_m_n(intel_crtc,
> - &intel_crtc->config.fdi_m_n, NULL);
> + &intel_crtc->config->fdi_m_n, NULL);
> }
>
> ironlake_set_pipeconf(crtc);
> @@ -4278,7 +4278,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
>
> - if (intel_crtc->config.has_pch_encoder) {
> + if (intel_crtc->config->has_pch_encoder) {
> /* Note: FDI PLL enabling _must_ be done before we enable the
> * cpu pipes, hence this is separate from all the other fdi/pch
> * enabling. */
> @@ -4299,7 +4299,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
>
> - if (intel_crtc->config.has_pch_encoder)
> + if (intel_crtc->config->has_pch_encoder)
> ironlake_pch_enable(crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> @@ -4365,19 +4365,19 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc_to_shared_dpll(intel_crtc))
> intel_enable_shared_dpll(intel_crtc);
>
> - if (intel_crtc->config.has_dp_encoder)
> + if (intel_crtc->config->has_dp_encoder)
> intel_dp_set_m_n(intel_crtc);
>
> intel_set_pipe_timings(intel_crtc);
>
> - if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
> - I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
> - intel_crtc->config.pixel_multiplier - 1);
> + if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
> + I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
> + intel_crtc->config->pixel_multiplier - 1);
> }
>
> - if (intel_crtc->config.has_pch_encoder) {
> + if (intel_crtc->config->has_pch_encoder) {
> intel_cpu_transcoder_set_m_n(intel_crtc,
> - &intel_crtc->config.fdi_m_n, NULL);
> + &intel_crtc->config->fdi_m_n, NULL);
> }
>
> haswell_set_pipeconf(crtc);
> @@ -4391,7 +4391,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
>
> - if (intel_crtc->config.has_pch_encoder) {
> + if (intel_crtc->config->has_pch_encoder) {
> intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> true);
> dev_priv->display.fdi_link_train(crtc);
> @@ -4416,10 +4416,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
>
> - if (intel_crtc->config.has_pch_encoder)
> + if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
>
> - if (intel_crtc->config.dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> @@ -4444,7 +4444,7 @@ static void skylake_pfit_disable(struct intel_crtc *crtc)
>
> /* To avoid upsetting the power well on haswell only disable the pfit if
> * it's in use. The hw state code will make sure we get this right. */
> - if (crtc->config.pch_pfit.enabled) {
> + if (crtc->config->pch_pfit.enabled) {
> I915_WRITE(PS_CTL(pipe), 0);
> I915_WRITE(PS_WIN_POS(pipe), 0);
> I915_WRITE(PS_WIN_SZ(pipe), 0);
> @@ -4459,7 +4459,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc)
>
> /* To avoid upsetting the power well on haswell only disable the pfit if
> * it's in use. The hw state code will make sure we get this right. */
> - if (crtc->config.pch_pfit.enabled) {
> + if (crtc->config->pch_pfit.enabled) {
> I915_WRITE(PF_CTL(pipe), 0);
> I915_WRITE(PF_WIN_POS(pipe), 0);
> I915_WRITE(PF_WIN_SZ(pipe), 0);
> @@ -4486,7 +4486,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->disable(encoder);
>
> - if (intel_crtc->config.has_pch_encoder)
> + if (intel_crtc->config->has_pch_encoder)
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> intel_disable_pipe(intel_crtc);
> @@ -4497,7 +4497,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
> if (encoder->post_disable)
> encoder->post_disable(encoder);
>
> - if (intel_crtc->config.has_pch_encoder) {
> + if (intel_crtc->config->has_pch_encoder) {
> ironlake_fdi_disable(crtc);
>
> ironlake_disable_pch_transcoder(dev_priv, pipe);
> @@ -4537,7 +4537,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>
> if (!intel_crtc->active)
> return;
> @@ -4552,12 +4552,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> encoder->disable(encoder);
> }
>
> - if (intel_crtc->config.has_pch_encoder)
> + if (intel_crtc->config->has_pch_encoder)
> intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> false);
> intel_disable_pipe(intel_crtc);
>
> - if (intel_crtc->config.dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, false);
>
> intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
> @@ -4569,7 +4569,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>
> intel_ddi_disable_pipe_clock(intel_crtc);
>
> - if (intel_crtc->config.has_pch_encoder) {
> + if (intel_crtc->config->has_pch_encoder) {
> lpt_disable_pch_transcoder(dev_priv);
> intel_ddi_fdi_disable(crtc);
> }
> @@ -4600,7 +4600,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc_state *pipe_config = &crtc->config;
> + struct intel_crtc_state *pipe_config = crtc->config;
>
> if (!pipe_config->gmch_pfit.control)
> return;
> @@ -4681,8 +4681,8 @@ static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
>
> mask = BIT(POWER_DOMAIN_PIPE(pipe));
> mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
> - if (intel_crtc->config.pch_pfit.enabled ||
> - intel_crtc->config.pch_pfit.force_thru)
> + if (intel_crtc->config->pch_pfit.enabled ||
> + intel_crtc->config->pch_pfit.force_thru)
> mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
>
> for_each_encoder_on_crtc(dev, crtc, intel_encoder)
> @@ -4986,12 +4986,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>
> if (!is_dsi) {
> if (IS_CHERRYVIEW(dev))
> - chv_prepare_pll(intel_crtc, &intel_crtc->config);
> + chv_prepare_pll(intel_crtc, intel_crtc->config);
> else
> - vlv_prepare_pll(intel_crtc, &intel_crtc->config);
> + vlv_prepare_pll(intel_crtc, intel_crtc->config);
> }
>
> - if (intel_crtc->config.has_dp_encoder)
> + if (intel_crtc->config->has_dp_encoder)
> intel_dp_set_m_n(intel_crtc);
>
> intel_set_pipe_timings(intel_crtc);
> @@ -5015,9 +5015,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>
> if (!is_dsi) {
> if (IS_CHERRYVIEW(dev))
> - chv_enable_pll(intel_crtc, &intel_crtc->config);
> + chv_enable_pll(intel_crtc, intel_crtc->config);
> else
> - vlv_enable_pll(intel_crtc, &intel_crtc->config);
> + vlv_enable_pll(intel_crtc, intel_crtc->config);
> }
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> @@ -5048,8 +5048,8 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
> - I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
> + I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
> + I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
> }
>
> static void i9xx_crtc_enable(struct drm_crtc *crtc)
> @@ -5067,7 +5067,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>
> i9xx_set_pll_dividers(intel_crtc);
>
> - if (intel_crtc->config.has_dp_encoder)
> + if (intel_crtc->config->has_dp_encoder)
> intel_dp_set_m_n(intel_crtc);
>
> intel_set_pipe_timings(intel_crtc);
> @@ -5119,7 +5119,7 @@ static void i9xx_pfit_disable(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (!crtc->config.gmch_pfit.control)
> + if (!crtc->config->gmch_pfit.control)
> return;
>
> assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -5418,7 +5418,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> return true;
> case PIPE_C:
> if (!pipe_has_enabled_pch(pipe_B_crtc) ||
> - pipe_B_crtc->config.fdi_lanes <= 2) {
> + pipe_B_crtc->config->fdi_lanes <= 2) {
> if (pipe_config->fdi_lanes > 2) {
> DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
> pipe_name(pipe), pipe_config->fdi_lanes);
> @@ -5816,7 +5816,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe = crtc->pipe;
> - enum transcoder transcoder = crtc->config.cpu_transcoder;
> + enum transcoder transcoder = crtc->config->cpu_transcoder;
>
> if (INTEL_INFO(dev)->gen >= 5) {
> I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
> @@ -5828,7 +5828,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> * registers are not unnecessarily accessed).
> */
> if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
> - crtc->config.has_drrs) {
> + crtc->config->has_drrs) {
> I915_WRITE(PIPE_DATA_M2(transcoder),
> TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
> I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> @@ -5845,11 +5845,11 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>
> void intel_dp_set_m_n(struct intel_crtc *crtc)
> {
> - if (crtc->config.has_pch_encoder)
> - intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
> + if (crtc->config->has_pch_encoder)
> + intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
> else
> - intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
> - &crtc->config.dp_m2_n2);
> + intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
> + &crtc->config->dp_m2_n2);
> }
>
> static void vlv_update_pll(struct intel_crtc *crtc,
> @@ -6217,9 +6217,9 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> struct drm_device *dev = intel_crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum pipe pipe = intel_crtc->pipe;
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config.base.adjusted_mode;
> + &intel_crtc->config->base.adjusted_mode;
> uint32_t crtc_vtotal, crtc_vblank_end;
> int vsyncshift = 0;
>
> @@ -6277,8 +6277,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> * always be the user's requested size.
> */
> I915_WRITE(PIPESRC(pipe),
> - ((intel_crtc->config.pipe_src_w - 1) << 16) |
> - (intel_crtc->config.pipe_src_h - 1));
> + ((intel_crtc->config->pipe_src_w - 1) << 16) |
> + (intel_crtc->config->pipe_src_h - 1));
> }
>
> static void intel_get_pipe_timings(struct intel_crtc *crtc,
> @@ -6354,17 +6354,17 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
> pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
>
> - if (intel_crtc->config.double_wide)
> + if (intel_crtc->config->double_wide)
> pipeconf |= PIPECONF_DOUBLE_WIDE;
>
> /* only g4x and later have fancy bpc/dither controls */
> if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> /* Bspec claims that we can't use dithering for 30bpp pipes. */
> - if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
> + if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
> pipeconf |= PIPECONF_DITHER_EN |
> PIPECONF_DITHER_TYPE_SP;
>
> - switch (intel_crtc->config.pipe_bpp) {
> + switch (intel_crtc->config->pipe_bpp) {
> case 18:
> pipeconf |= PIPECONF_6BPC;
> break;
> @@ -6389,7 +6389,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> }
> }
>
> - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> if (INTEL_INFO(dev)->gen < 4 ||
> intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
> pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> @@ -6398,7 +6398,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> } else
> pipeconf |= PIPECONF_PROGRESSIVE;
>
> - if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
> + if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
> pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
>
> I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
> @@ -7126,7 +7126,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
>
> val = 0;
>
> - switch (intel_crtc->config.pipe_bpp) {
> + switch (intel_crtc->config->pipe_bpp) {
> case 18:
> val |= PIPECONF_6BPC;
> break;
> @@ -7144,15 +7144,15 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
> BUG();
> }
>
> - if (intel_crtc->config.dither)
> + if (intel_crtc->config->dither)
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> val |= PIPECONF_INTERLACED_ILK;
> else
> val |= PIPECONF_PROGRESSIVE;
>
> - if (intel_crtc->config.limited_color_range)
> + if (intel_crtc->config->limited_color_range)
> val |= PIPECONF_COLOR_RANGE_SELECT;
>
> I915_WRITE(PIPECONF(pipe), val);
> @@ -7181,7 +7181,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
> * consideration.
> */
>
> - if (intel_crtc->config.limited_color_range)
> + if (intel_crtc->config->limited_color_range)
> coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
>
> /*
> @@ -7205,7 +7205,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
> if (INTEL_INFO(dev)->gen > 6) {
> uint16_t postoff = 0;
>
> - if (intel_crtc->config.limited_color_range)
> + if (intel_crtc->config->limited_color_range)
> postoff = (16 * (1 << 12) / 255) & 0x1fff;
>
> I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
> @@ -7216,7 +7216,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
> } else {
> uint32_t mode = CSC_MODE_YUV_TO_RGB;
>
> - if (intel_crtc->config.limited_color_range)
> + if (intel_crtc->config->limited_color_range)
> mode |= CSC_BLACK_SCREEN_OFFSET;
>
> I915_WRITE(PIPE_CSC_MODE(pipe), mode);
> @@ -7229,15 +7229,15 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum pipe pipe = intel_crtc->pipe;
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> uint32_t val;
>
> val = 0;
>
> - if (IS_HASWELL(dev) && intel_crtc->config.dither)
> + if (IS_HASWELL(dev) && intel_crtc->config->dither)
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> val |= PIPECONF_INTERLACED_ILK;
> else
> val |= PIPECONF_PROGRESSIVE;
> @@ -7251,7 +7251,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
> if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
> val = 0;
>
> - switch (intel_crtc->config.pipe_bpp) {
> + switch (intel_crtc->config->pipe_bpp) {
> case 18:
> val |= PIPEMISC_DITHER_6_BPC;
> break;
> @@ -7269,7 +7269,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
> BUG();
> }
>
> - if (intel_crtc->config.dither)
> + if (intel_crtc->config->dither)
> val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
>
> I915_WRITE(PIPEMISC(pipe), val);
> @@ -7530,7 +7530,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
> * registers are not unnecessarily read).
> */
> if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
> - crtc->config.has_drrs) {
> + crtc->config->has_drrs) {
> m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
> m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
> m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
> @@ -8282,10 +8282,10 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
> if (on)
> base = intel_crtc->cursor_addr;
>
> - if (x >= intel_crtc->config.pipe_src_w)
> + if (x >= intel_crtc->config->pipe_src_w)
> base = 0;
>
> - if (y >= intel_crtc->config.pipe_src_h)
> + if (y >= intel_crtc->config->pipe_src_h)
> base = 0;
>
> if (x < 0) {
> @@ -8812,7 +8812,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> struct drm_display_mode *mode;
> struct intel_crtc_state pipe_config;
> int htot = I915_READ(HTOTAL(cpu_transcoder));
> @@ -10769,11 +10769,11 @@ check_crtc_state(struct drm_device *dev)
> "(expected %i, found %i)\n", crtc->active, active);
>
> if (active &&
> - !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
> + !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
> WARN(1, "pipe state doesn't match!\n");
> intel_dump_pipe_config(crtc, &pipe_config,
> "[hw state]");
> - intel_dump_pipe_config(crtc, &crtc->config,
> + intel_dump_pipe_config(crtc, crtc->config,
> "[sw state]");
> }
> }
> @@ -10873,7 +10873,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
> * one to the value.
> */
> if (IS_GEN2(dev)) {
> - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
> + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
> int vtotal;
>
> vtotal = mode->crtc_vtotal;
> @@ -10921,6 +10921,13 @@ out:
> return pipe_config;
> }
>
> +static void intel_crtc_set_state(struct intel_crtc *crtc,
> + struct intel_crtc_state *crtc_state)
> +{
> + kfree(crtc->config);
> + crtc->config = crtc_state;
> +}
> +
> static int __intel_set_mode(struct drm_crtc *crtc,
> struct drm_display_mode *mode,
> int x, int y, struct drm_framebuffer *fb,
> @@ -11000,7 +11007,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> crtc->mode = *mode;
> /* mode_set/enable/disable functions rely on a correct pipe
> * config. */
> - to_intel_crtc(crtc)->config = *pipe_config;
> + intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
>
> /*
> * Calculate and store various constants which
> @@ -11044,7 +11051,6 @@ done:
> if (ret && crtc->enabled)
> crtc->mode = *saved_mode;
>
> - kfree(pipe_config);
> kfree(saved_mode);
> return ret;
> }
> @@ -11461,7 +11467,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
> goto fail;
> } else if (pipe_config) {
> if (pipe_config->has_audio !=
> - to_intel_crtc(set->crtc)->config.has_audio)
> + to_intel_crtc(set->crtc)->config->has_audio)
> config->mode_changed = true;
>
> /*
> @@ -11886,8 +11892,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>
> state.clip.x1 = 0;
> state.clip.y1 = 0;
> - state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
> - state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
> + state.clip.x2 = intel_crtc->active ? intel_crtc->config->pipe_src_w : 0;
> + state.clip.y2 = intel_crtc->active ? intel_crtc->config->pipe_src_h : 0;
>
> state.orig_src = state.src;
> state.orig_dst = state.dst;
> @@ -12169,6 +12175,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *crtc_state = NULL;
> struct drm_plane *primary = NULL;
> struct drm_plane *cursor = NULL;
> int i, ret;
> @@ -12177,6 +12184,11 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
> if (intel_crtc == NULL)
> return;
>
> + crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
> + if (!crtc_state)
> + goto fail;
> + intel_crtc_set_state(intel_crtc, crtc_state);
> +
> primary = intel_primary_plane_create(dev, pipe);
> if (!primary)
> goto fail;
> @@ -12229,6 +12241,7 @@ fail:
> drm_plane_cleanup(primary);
> if (cursor)
> drm_plane_cleanup(cursor);
> + kfree(crtc_state);
> kfree(intel_crtc);
> }
>
> @@ -13131,7 +13144,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
> u32 reg;
>
> /* Clear any frame start delays used for debugging left by the BIOS */
> - reg = PIPECONF(crtc->config.cpu_transcoder);
> + reg = PIPECONF(crtc->config->cpu_transcoder);
> I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
>
> /* restore vblank interrupts to correct state */
> @@ -13335,12 +13348,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> int i;
>
> for_each_intel_crtc(dev, crtc) {
> - memset(&crtc->config, 0, sizeof(crtc->config));
> + memset(crtc->config, 0, sizeof(*crtc->config));
>
> - crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
> + crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
>
> crtc->active = dev_priv->display.get_pipe_config(crtc,
> - &crtc->config);
> + crtc->config);
>
> crtc->base.enabled = crtc->active;
> crtc->primary_enabled = primary_get_hw_state(crtc);
> @@ -13377,7 +13390,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> if (encoder->get_hw_state(encoder, &pipe)) {
> crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> encoder->base.crtc = &crtc->base;
> - encoder->get_config(encoder, &crtc->config);
> + encoder->get_config(encoder, crtc->config);
> } else {
> encoder->base.crtc = NULL;
> }
> @@ -13427,7 +13440,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
> */
> for_each_intel_crtc(dev, crtc) {
> if (crtc->active && i915.fastboot) {
> - intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
> + intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
> DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
> crtc->base.base.id);
> drm_mode_debug_printmodeline(&crtc->base.mode);
> @@ -13442,7 +13455,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
> for_each_pipe(dev_priv, pipe) {
> crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> intel_sanitize_crtc(crtc);
> - intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
> + intel_dump_pipe_config(crtc, crtc->config, "[setup_hw_state]");
> }
>
> for (i = 0; i < dev_priv->num_shared_dpll; i++) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 67cdbe8..d6f0d90 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1295,11 +1295,11 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 dpa_ctl;
>
> - DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
> + DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config->port_clock);
> dpa_ctl = I915_READ(DP_A);
> dpa_ctl &= ~DP_PLL_FREQ_MASK;
>
> - if (crtc->config.port_clock == 162000) {
> + if (crtc->config->port_clock == 162000) {
> /* For a long time we've carried around a ILK-DevA w/a for the
> * 160MHz clock. If we're really unlucky, it's still required.
> */
> @@ -1324,7 +1324,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = dp_to_dig_port(intel_dp)->port;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
>
> /*
> * There are four kinds of DP registers:
> @@ -1352,7 +1352,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
> intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
> intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
>
> - if (crtc->config.has_audio)
> + if (crtc->config->has_audio)
> intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
>
> /* Split out the IBX/CPU vs CPT settings */
> @@ -2102,7 +2102,7 @@ static void intel_disable_dp(struct intel_encoder *encoder)
> struct drm_device *dev = encoder->base.dev;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>
> - if (crtc->config.has_audio)
> + if (crtc->config->has_audio)
> intel_audio_codec_disable(encoder);
>
> if (HAS_PSR(dev) && !HAS_DDI(dev))
> @@ -2312,7 +2312,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
> intel_dp_complete_link_train(intel_dp);
> intel_dp_stop_link_train(intel_dp);
>
> - if (crtc->config.has_audio) {
> + if (crtc->config->has_audio) {
> DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
> pipe_name(crtc->pipe));
> intel_audio_codec_enable(encoder);
> @@ -4780,7 +4780,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> return;
> }
>
> - config = &intel_crtc->config;
> + config = intel_crtc->config;
>
> if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
> DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
> @@ -4802,7 +4802,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> }
>
> if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
> - reg = PIPECONF(intel_crtc->config.cpu_transcoder);
> + reg = PIPECONF(intel_crtc->config->cpu_transcoder);
> val = I915_READ(reg);
> if (index > DRRS_HIGH_RR) {
> val |= PIPECONF_EDP_RR_MODE_SWITCH;
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 257aca1..28b6ee4 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -157,7 +157,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
> if (intel_dp->active_mst_links == 0) {
> enum port port = intel_ddi_get_encoder_port(encoder);
>
> - I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config.ddi_pll_sel);
> + I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config->ddi_pll_sel);
>
> intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
>
> @@ -170,7 +170,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
> }
>
> ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr,
> - intel_mst->port, intel_crtc->config.pbn, &slots);
> + intel_mst->port, intel_crtc->config->pbn,
> + &slots);
> if (ret == false) {
> DRM_ERROR("failed to allocate vcpi\n");
> return;
> @@ -223,7 +224,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> u32 temp, flags = 0;
>
> pipe_config->has_dp_encoder = true;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 175b853..01d6fa1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -439,7 +439,7 @@ struct intel_crtc {
> uint32_t cursor_base;
>
> struct intel_plane_config plane_config;
> - struct intel_crtc_state config;
> + struct intel_crtc_state *config;
> bool new_enabled;
>
> /* reset counter value when the last flip was submitted */
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 25291e9..5d9ec7b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -232,7 +232,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> I915_WRITE(DPLL(pipe), tmp);
>
> /* update the hw state for DPLL */
> - intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
> + intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
> DPLL_REFA_CLK_ENABLE_VLV;
>
> tmp = I915_READ(DSPCLK_GATE_D);
> @@ -494,7 +494,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> - unsigned int bpp = intel_crtc->config.pipe_bpp;
> + unsigned int bpp = intel_crtc->config->pipe_bpp;
> unsigned int lane_count = intel_dsi->lane_count;
>
> u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
> @@ -549,9 +549,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config.base.adjusted_mode;
> + &intel_crtc->config->base.adjusted_mode;
> enum port port;
> - unsigned int bpp = intel_crtc->config.pipe_bpp;
> + unsigned int bpp = intel_crtc->config->pipe_bpp;
> u32 val, tmp;
> u16 mode_hdisplay;
>
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index 108f058..706ab99 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -186,8 +186,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
> u32 temp = I915_READ(dvo_reg);
>
> intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
> - &crtc->config.base.mode,
> - &crtc->config.base.adjusted_mode);
> + &crtc->config->base.mode,
> + &crtc->config->base.adjusted_mode);
>
> I915_WRITE(dvo_reg, temp | DVO_ENABLE);
> I915_READ(dvo_reg);
> @@ -221,7 +221,7 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
> /* We call connector dpms manually below in case pipe dpms doesn't
> * change due to cloning. */
> if (mode == DRM_MODE_DPMS_ON) {
> - config = &to_intel_crtc(crtc)->config;
> + config = to_intel_crtc(crtc)->config;
>
> intel_dvo->base.connectors_active = true;
>
> @@ -295,7 +295,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder)
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
> struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> int pipe = crtc->pipe;
> u32 dvo_val;
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> index 1a9a727..f426e7c 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -431,7 +431,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
> DRM_DEBUG_KMS("looking for current mode on connector %s\n",
> connector->name);
> intel_mode_from_pipe_config(&encoder->crtc->hwmode,
> - &to_intel_crtc(encoder->crtc)->config);
> + to_intel_crtc(encoder->crtc)->config);
> modes[i] = &encoder->crtc->hwmode;
> }
> crtcs[i] = new_crtc;
> @@ -563,7 +563,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
> * pipe. Note we need to use the selected fb's pitch and bpp
> * rather than the current pipe's, since they differ.
> */
> - cur_size = intel_crtc->config.base.adjusted_mode.crtc_hdisplay;
> + cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay;
> cur_size = cur_size * fb->base.bits_per_pixel / 8;
> if (fb->base.pitches[0] < cur_size) {
> DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n",
> @@ -574,13 +574,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
> break;
> }
>
> - cur_size = intel_crtc->config.base.adjusted_mode.crtc_vdisplay;
> + cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
> cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1);
> cur_size *= fb->base.pitches[0];
> DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
> pipe_name(intel_crtc->pipe),
> - intel_crtc->config.base.adjusted_mode.crtc_hdisplay,
> - intel_crtc->config.base.adjusted_mode.crtc_vdisplay,
> + intel_crtc->config->base.adjusted_mode.crtc_hdisplay,
> + intel_crtc->config->base.adjusted_mode.crtc_vdisplay,
> fb->base.bits_per_pixel,
> cur_size);
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 02ff3e2..200a0e7 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -337,13 +337,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
> + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
> u32 data_reg;
> int i;
> u32 val = I915_READ(ctl_reg);
>
> data_reg = hsw_infoframe_data_reg(type,
> - intel_crtc->config.cpu_transcoder,
> + intel_crtc->config->cpu_transcoder,
> dev_priv);
> if (data_reg == 0)
> return;
> @@ -371,7 +371,7 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
> + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
> u32 val = I915_READ(ctl_reg);
>
> return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
> @@ -436,7 +436,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
> }
>
> if (intel_hdmi->rgb_quant_range_selectable) {
> - if (intel_crtc->config.limited_color_range)
> + if (intel_crtc->config->limited_color_range)
> frame.avi.quantization_range =
> HDMI_QUANTIZATION_RANGE_LIMITED;
> else
> @@ -672,7 +672,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
> struct drm_i915_private *dev_priv = encoder->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> - u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
> + u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
> u32 val = I915_READ(reg);
>
> assert_hdmi_port_disabled(intel_hdmi);
> @@ -700,7 +700,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> - struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
> u32 hdmi_val;
>
> hdmi_val = SDVO_ENCODING_HDMI;
> @@ -711,12 +711,12 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
>
> - if (crtc->config.pipe_bpp > 24)
> + if (crtc->config->pipe_bpp > 24)
> hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
> else
> hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
>
> - if (crtc->config.has_hdmi_sink)
> + if (crtc->config->has_hdmi_sink)
> hdmi_val |= HDMI_MODE_SELECT_HDMI;
>
> if (HAS_PCH_CPT(dev))
> @@ -814,7 +814,7 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
> u32 temp;
> u32 enable_bits = SDVO_ENABLE;
>
> - if (intel_crtc->config.has_audio)
> + if (intel_crtc->config->has_audio)
> enable_bits |= SDVO_AUDIO_ENABLE;
>
> temp = I915_READ(intel_hdmi->hdmi_reg);
> @@ -845,8 +845,8 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
> POSTING_READ(intel_hdmi->hdmi_reg);
> }
>
> - if (intel_crtc->config.has_audio) {
> - WARN_ON(!intel_crtc->config.has_hdmi_sink);
> + if (intel_crtc->config->has_audio) {
> + WARN_ON(!intel_crtc->config->has_hdmi_sink);
> DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
> pipe_name(intel_crtc->pipe));
> intel_audio_codec_enable(encoder);
> @@ -866,7 +866,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
> u32 temp;
> u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
>
> - if (crtc->config.has_audio)
> + if (crtc->config->has_audio)
> intel_audio_codec_disable(encoder);
>
> temp = I915_READ(intel_hdmi->hdmi_reg);
> @@ -1252,12 +1252,12 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config.base.adjusted_mode;
> + &intel_crtc->config->base.adjusted_mode;
>
> intel_hdmi_prepare(encoder);
>
> intel_hdmi->set_infoframes(&encoder->base,
> - intel_crtc->config.has_hdmi_sink,
> + intel_crtc->config->has_hdmi_sink,
> adjusted_mode);
> }
>
> @@ -1270,7 +1270,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
> struct intel_crtc *intel_crtc =
> to_intel_crtc(encoder->base.crtc);
> struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config.base.adjusted_mode;
> + &intel_crtc->config->base.adjusted_mode;
> enum dpio_channel port = vlv_dport_to_channel(dport);
> int pipe = intel_crtc->pipe;
> u32 val;
> @@ -1302,7 +1302,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
> mutex_unlock(&dev_priv->dpio_lock);
>
> intel_hdmi->set_infoframes(&encoder->base,
> - intel_crtc->config.has_hdmi_sink,
> + intel_crtc->config->has_hdmi_sink,
> adjusted_mode);
>
> intel_enable_hdmi(encoder);
> @@ -1467,7 +1467,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> struct intel_crtc *intel_crtc =
> to_intel_crtc(encoder->base.crtc);
> struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config.base.adjusted_mode;
> + &intel_crtc->config->base.adjusted_mode;
> enum dpio_channel ch = vlv_dport_to_channel(dport);
> int pipe = intel_crtc->pipe;
> int data, i;
> @@ -1593,7 +1593,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> mutex_unlock(&dev_priv->dpio_lock);
>
> intel_hdmi->set_infoframes(&encoder->base,
> - intel_crtc->config.has_hdmi_sink,
> + intel_crtc->config->has_hdmi_sink,
> adjusted_mode);
>
> intel_enable_hdmi(encoder);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 9d174cf..c7c6414 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -139,7 +139,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config.base.adjusted_mode;
> + &crtc->config->base.adjusted_mode;
> int pipe = crtc->pipe;
> u32 temp;
>
> @@ -167,7 +167,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
>
> /* set the corresponsding LVDS_BORDER bit */
> temp &= ~LVDS_BORDER_ENABLE;
> - temp |= crtc->config.gmch_pfit.lvds_border_bits;
> + temp |= crtc->config->gmch_pfit.lvds_border_bits;
> /* Set the B0-B3 data pairs corresponding to whether we're going to
> * set the DPLLs for dual-channel mode or not.
> */
> @@ -190,7 +190,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
> if (INTEL_INFO(dev)->gen == 4) {
> /* Bspec wording suggests that LVDS port dithering only exists
> * for 18bpp panels. */
> - if (crtc->config.dither && crtc->config.pipe_bpp == 18)
> + if (crtc->config->dither && crtc->config->pipe_bpp == 18)
> temp |= LVDS_ENABLE_DITHER;
> else
> temp &= ~LVDS_ENABLE_DITHER;
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 973c9de..f93dfc1 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -856,7 +856,7 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
> return -EINVAL;
>
> /* can't use the overlay with double wide pipe */
> - if (crtc->config.double_wide)
> + if (crtc->config->double_wide)
> return -EINVAL;
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 47b23b7..22e49f4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -574,7 +574,7 @@ void intel_update_fbc(struct drm_device *dev)
> intel_crtc = to_intel_crtc(crtc);
> fb = crtc->primary->fb;
> obj = intel_fb_obj(fb);
> - adjusted_mode = &intel_crtc->config.base.adjusted_mode;
> + adjusted_mode = &intel_crtc->config->base.adjusted_mode;
>
> if (i915.enable_fbc < 0) {
> if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
> @@ -604,8 +604,8 @@ void intel_update_fbc(struct drm_device *dev)
> max_width = 2048;
> max_height = 1536;
> }
> - if (intel_crtc->config.pipe_src_w > max_width ||
> - intel_crtc->config.pipe_src_h > max_height) {
> + if (intel_crtc->config->pipe_src_w > max_width ||
> + intel_crtc->config->pipe_src_h > max_height) {
> if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
> DRM_DEBUG_KMS("mode too large for compression, disabling\n");
> goto out_disable;
> @@ -1157,7 +1157,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
> int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> int clock;
>
> - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
> + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> clock = adjusted_mode->crtc_clock;
>
> /* Display SR */
> @@ -1226,10 +1226,10 @@ static bool g4x_compute_wm0(struct drm_device *dev,
> return false;
> }
>
> - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
> + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> clock = adjusted_mode->crtc_clock;
> htotal = adjusted_mode->crtc_htotal;
> - hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
> + hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> pixel_size = crtc->primary->fb->bits_per_pixel / 8;
>
> /* Use the small buffer method to calculate plane watermark */
> @@ -1313,10 +1313,10 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> }
>
> crtc = intel_get_crtc_for_plane(dev, plane);
> - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
> + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> clock = adjusted_mode->crtc_clock;
> htotal = adjusted_mode->crtc_htotal;
> - hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
> + hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> pixel_size = crtc->primary->fb->bits_per_pixel / 8;
>
> line_time_us = max(htotal * 1000 / clock, 1);
> @@ -1347,7 +1347,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
> {
> struct drm_device *dev = crtc->dev;
> int entries;
> - int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
> + int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
>
> if (WARN(clock == 0, "Pixel clock is zero!\n"))
> return false;
> @@ -1677,10 +1677,10 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
> /* self-refresh has much higher latency */
> static const int sr_latency_ns = 12000;
> const struct drm_display_mode *adjusted_mode =
> - &to_intel_crtc(crtc)->config.base.adjusted_mode;
> + &to_intel_crtc(crtc)->config->base.adjusted_mode;
> int clock = adjusted_mode->crtc_clock;
> int htotal = adjusted_mode->crtc_htotal;
> - int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
> + int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> unsigned long line_time_us;
> int entries;
> @@ -1762,7 +1762,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> if (IS_GEN2(dev))
> cpp = 4;
>
> - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
> + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> wm_info, fifo_size, cpp,
> pessimal_latency_ns);
> @@ -1784,7 +1784,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> if (IS_GEN2(dev))
> cpp = 4;
>
> - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
> + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> wm_info, fifo_size, cpp,
> pessimal_latency_ns);
> @@ -1823,10 +1823,10 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> /* self-refresh has much higher latency */
> static const int sr_latency_ns = 6000;
> const struct drm_display_mode *adjusted_mode =
> - &to_intel_crtc(enabled)->config.base.adjusted_mode;
> + &to_intel_crtc(enabled)->config->base.adjusted_mode;
> int clock = adjusted_mode->crtc_clock;
> int htotal = adjusted_mode->crtc_htotal;
> - int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
> + int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
> int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
> unsigned long line_time_us;
> int entries;
> @@ -1879,7 +1879,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
> if (crtc == NULL)
> return;
>
> - adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
> + adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> &i845_wm_info,
> dev_priv->display.get_fifo_size(dev, 0),
> @@ -1898,17 +1898,17 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t pixel_rate;
>
> - pixel_rate = intel_crtc->config.base.adjusted_mode.crtc_clock;
> + pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
>
> /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
> * adjust the pixel_rate here. */
>
> - if (intel_crtc->config.pch_pfit.enabled) {
> + if (intel_crtc->config->pch_pfit.enabled) {
> uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
> - uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
> + uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
>
> - pipe_w = intel_crtc->config.pipe_src_w;
> - pipe_h = intel_crtc->config.pipe_src_h;
> + pipe_w = intel_crtc->config->pipe_src_w;
> + pipe_h = intel_crtc->config->pipe_src_h;
> pfit_w = (pfit_size >> 16) & 0xFFFF;
> pfit_h = pfit_size & 0xFFFF;
> if (pipe_w < pfit_w)
> @@ -2261,7 +2261,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
> + struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
> u32 linetime, ips_linetime;
>
> if (!intel_crtc_active(crtc))
> @@ -2521,11 +2521,11 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
> return;
>
> p->active = true;
> - p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
> + p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
> p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
> p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
> p->cur.bytes_per_pixel = 4;
> - p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
> + p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
> p->cur.horiz_pixels = intel_crtc->cursor_width;
> /* TODO: for now, assume primary and cursor planes are always enabled. */
> p->pri.enabled = true;
> @@ -3265,8 +3265,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
>
> p->active = intel_crtc_active(crtc);
> if (p->active) {
> - p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
> - p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
> + p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
> + p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
>
> /*
> * For now, assume primary and cursor planes are always enabled.
> @@ -3274,8 +3274,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> p->plane[0].enabled = true;
> p->plane[0].bytes_per_pixel =
> crtc->primary->fb->bits_per_pixel / 8;
> - p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w;
> - p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h;
> + p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
> + p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
>
> p->cursor.enabled = true;
> p->cursor.bytes_per_pixel = 4;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index b8713e4..494b132 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -79,8 +79,8 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> struct drm_device *dev = dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> - u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
> - u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
> + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
> + u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
> uint32_t *data = (uint32_t *) vsc_psr;
> unsigned int i;
>
> @@ -274,13 +274,13 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> if (IS_BROADWELL(dev))
> goto out;
>
> - if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
> + if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
> S3D_ENABLE) {
> DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
> return false;
> }
>
> - if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> + if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> return false;
> }
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index e4d5da5..8c8d807 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1007,7 +1007,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
> }
>
> if (intel_sdvo->rgb_quant_range_selectable) {
> - if (intel_crtc->config.limited_color_range)
> + if (intel_crtc->config->limited_color_range)
> frame.avi.quantization_range =
> HDMI_QUANTIZATION_RANGE_LIMITED;
> else
> @@ -1181,8 +1181,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
> struct drm_display_mode *adjusted_mode =
> - &crtc->config.base.adjusted_mode;
> - struct drm_display_mode *mode = &crtc->config.base.mode;
> + &crtc->config->base.adjusted_mode;
> + struct drm_display_mode *mode = &crtc->config->base.mode;
> struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
> u32 sdvox;
> struct intel_sdvo_in_out_map in_out;
> @@ -1224,7 +1224,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
> if (!intel_sdvo_set_target_input(intel_sdvo))
> return;
>
> - if (crtc->config.has_hdmi_sink) {
> + if (crtc->config->has_hdmi_sink) {
> intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
> intel_sdvo_set_colorimetry(intel_sdvo,
> SDVO_COLORIMETRY_RGB256);
> @@ -1244,7 +1244,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
> DRM_INFO("Setting input timings on %s failed\n",
> SDVO_NAME(intel_sdvo));
>
> - switch (crtc->config.pixel_multiplier) {
> + switch (crtc->config->pixel_multiplier) {
> default:
> WARN(1, "unknown pixel mutlipler specified\n");
> case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
> @@ -1259,7 +1259,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
> /* The real mode polarity is set by the SDVO commands, using
> * struct intel_sdvo_dtd. */
> sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
> - if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range)
> + if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
> sdvox |= HDMI_COLOR_RANGE_16_235;
> if (INTEL_INFO(dev)->gen < 5)
> sdvox |= SDVO_BORDER_ENABLE;
> @@ -1289,7 +1289,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
> } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
> /* done in crtc_mode_set as it lives inside the dpll register */
> } else {
> - sdvox |= (crtc->config.pixel_multiplier - 1)
> + sdvox |= (crtc->config->pixel_multiplier - 1)
> << SDVO_PORT_MULTIPLY_SHIFT;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 454b25d..937bd72 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -79,7 +79,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
> bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
> {
> struct drm_device *dev = crtc->base.dev;
> - const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
> + const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
> enum pipe pipe = crtc->pipe;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config
2014-12-11 12:38 [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync Ander Conselvan de Oliveira
` (6 preceding siblings ...)
2014-12-11 12:38 ` [PATCH 7/8] drm/i915: Make intel_crtc->config a pointer Ander Conselvan de Oliveira
@ 2014-12-11 12:38 ` Ander Conselvan de Oliveira
2014-12-11 12:49 ` shuang.he
7 siblings, 1 reply; 20+ messages in thread
From: Ander Conselvan de Oliveira @ 2014-12-11 12:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, shuang.he
So that atomic operations will reference the right crtc state.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 462f22a..20b9e9b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10926,6 +10926,7 @@ static void intel_crtc_set_state(struct intel_crtc *crtc,
{
kfree(crtc->config);
crtc->config = crtc_state;
+ crtc->base.state = &crtc_state->base;
}
static int __intel_set_mode(struct drm_crtc *crtc,
--
1.9.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config
2014-12-11 12:38 ` [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config Ander Conselvan de Oliveira
@ 2014-12-11 12:49 ` shuang.he
0 siblings, 0 replies; 20+ messages in thread
From: shuang.he @ 2014-12-11 12:49 UTC (permalink / raw)
To: shuang.he, intel-gfx, ander.conselvan.de.oliveira
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK +1-6 364/366 359/366
SNB 448/450 448/450
IVB 497/498 497/498
BYT 289/289 289/289
HSW 563/564 563/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*ILK igt_kms_pipe_crc_basic_bad-source PASS(3, M26) DMESG_WARN(1, M26)
*ILK igt_kms_setmode_invalid-clone-exclusive-crtc PASS(5, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible PASS(7, M26) DMESG_WARN(1, M26)
*ILK igt_kms_render_direct-render PASS(7, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_flip-vs-panning DMESG_WARN(1, M26)PASS(7, M26) NSPT(1, M26)
ILK igt_kms_flip_plain-flip-fb-recreate-interruptible DMESG_WARN(1, M26)PASS(3, M26) DMESG_WARN(1, M26)
ILK igt_kms_flip_wf_vblank-ts-check DMESG_WARN(7, M26)PASS(22, M26M37) PASS(1, M26)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 20+ messages in thread