Re: [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating

[Damien Lespiau <damien.lespiau@intel.com>]

On Fri, Jan 16, 2015 at 06:07:27PM +0000, Damien Lespiau wrote:
> From: Zhe Wang <zhe1.wang@intel.com>
> 
> Enable coarse power gating for Gen9. This feature allows render and
> media engine to enter RC6 independently. Policies are configured
> together with RC6. This feature will only be enabled when RC6 is
> enabled.
> 
> Signed-off-by: Zhe Wang <zhe1.wang@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cb96041..3d08f9d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6065,6 +6065,9 @@ enum skl_disp_power_wells {
>  #define GEN6_PMINTRMSK				0xA168
>  #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
>  #define VLV_PWRDWNUPCTL				0xA294
> +#define GEN9_MEDIA_PG_IDLE_HYSTERESIS		0xA0C4
> +#define GEN9_RENDER_PG_IDLE_HYSTERESIS		0xA0C8
> +#define GEN9_PG_ENABLE				0xA210
>  
>  #define VLV_CHICKEN_3				(VLV_DISPLAY_BASE + 0x7040C)
>  #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f40b8f2..71bf4f4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3892,6 +3892,7 @@ static void gen9_disable_rps(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	I915_WRITE(GEN6_RC_CONTROL, 0);
> +	I915_WRITE(GEN9_PG_ENABLE, 0);
>  }
>  
>  static void gen6_disable_rps(struct drm_device *dev)
> @@ -4081,6 +4082,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  	I915_WRITE(GEN6_RC_SLEEP, 0);
>  	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>  
> +	/* 2c: Program Coarse Power Gating Policies. */
> +	I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> +	I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
> +
>  	/* 3a: Enable RC6 */
>  	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
>  		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> @@ -4090,6 +4095,9 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  				   GEN6_RC_CTL_EI_MODE(1) |
>  				   rc6_mask);
>  
> +	/* 3b: Enable Coarse Power Gating only when RC6 is enabled */
> +	I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
> +
>  	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>  
>  }
> -- 
> 1.8.3.1
> 
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