Re: [PATCH 3/7] drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Jan 20, 2015 at 08:45:50AM +0530, Deepak S wrote:
> 
> On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable
> > the RP down timeout interrupt, and says that the timeout value is hence
> > not used. We do enable that interrupt currently though, so leaving the
> > timeout as 0 results in very poor performance as the GPU frequency keeps
> > dropping constantly. So just program the register with the recommended
> > value.
> >
> > Leaving the interrupt enabled doesn't seem to do any harm so far. So
> > I've decided to leave it on for now, just to avoid making CHV a
> > special case.
> >
> > This fixes the performance regression from:
> >   commit 5a0afd4b78ec23f27f5d486ac3d102c2e8d66bd7
> >   Author: Deepak S <deepak.s@linux.intel.com>
> >   Date:   Sat Dec 13 11:43:27 2014 +0530
> >
> >      drm/i915/chv: Use timeout mode for RC6 on chv
> >
> > Cc: Deepak S <deepak.s@linux.intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_pm.c | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ee9a5f9..8c7a07d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4743,6 +4743,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
> >   	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
> >   
> >   	/* 4 Program defaults and thresholds for RPS*/
> > +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> 
> I agree programing RP_DOWN_TIMEOUT Can cause the perf issue. I am surprised why we are not seeing similar issues with RC6 EI?

My observation running xonotic was that the freq did seem to drop in
EI mode too (as it should since the TO vs. EI is about RC not RP), but
somehow it didn't impact performance. I can't really explain why.
RC6 residency was a flat 0 with EI, and 5-20% with TO. With the fix
performace was the more or less the same in both cases, without the
fix TO mode suffered a 40% performance drop whereas EI didn't.

> 
> anways, we do not use GEN6_RP_DOWN_TIMEOUT in chv. Programing it's value to default should not harm

Except we do use GEN6_RP_DOWN_TIMEOUT, as in we enable the relevant
interrupt. I did also test a patch that left GEN6_RP_DOWN_TIMEOUT at 0,
and instead disabled the interrupt, and that also fixed the performance
bug. But I wanted to avoid making CHV even more of a special case, so
I've left the interrupt enabled, at least for now.

> Reviewed-by: Deepak S <deepak.s@intel.com>
> 
> >   	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> >   	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
> >   	I915_WRITE(GEN6_RP_UP_EI, 66000);

-- 
Ville Syrjälä
Intel OTC
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