* [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode()
@ 2015-01-29 14:55 Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 2/4] drm/i915: Move pll new_config field into intel_atomic_state Ander Conselvan de Oliveira
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Ander Conselvan de Oliveira @ 2015-01-29 14:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
This simplifies __intel_set_mode() a little.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++------------
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 423ef95..3d220a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11021,6 +11021,36 @@ out:
return pipe_config;
}
+static int __intel_set_mode_setup_plls(struct drm_device *dev,
+ unsigned modeset_pipes,
+ unsigned disable_pipes)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ unsigned clear_pipes = modeset_pipes | disable_pipes;
+ struct intel_crtc *intel_crtc;
+ int ret = 0;
+
+ if (!dev_priv->display.crtc_compute_clock)
+ return 0;
+
+ ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
+ if (ret)
+ goto done;
+
+ for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
+ struct intel_crtc_state *state = intel_crtc->new_config;
+ ret = dev_priv->display.crtc_compute_clock(intel_crtc,
+ state);
+ if (ret) {
+ intel_shared_dpll_abort_config(dev_priv);
+ goto done;
+ }
+ }
+
+done:
+ return ret;
+}
+
static int __intel_set_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode,
int x, int y, struct drm_framebuffer *fb,
@@ -11058,23 +11088,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
prepare_pipes &= ~disable_pipes;
}
- if (dev_priv->display.crtc_compute_clock) {
- unsigned clear_pipes = modeset_pipes | disable_pipes;
-
- ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
- if (ret)
- goto done;
-
- for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
- struct intel_crtc_state *state = intel_crtc->new_config;
- ret = dev_priv->display.crtc_compute_clock(intel_crtc,
- state);
- if (ret) {
- intel_shared_dpll_abort_config(dev_priv);
- goto done;
- }
- }
- }
+ ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
+ if (ret)
+ goto done;
for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
intel_crtc_disable(&intel_crtc->base);
--
2.1.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] drm/i915: Move pll new_config field into intel_atomic_state
2015-01-29 14:55 [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode() Ander Conselvan de Oliveira
@ 2015-01-29 14:55 ` Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 3/4] drm/i915: Move current pll config to shared global state Ander Conselvan de Oliveira
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Ander Conselvan de Oliveira @ 2015-01-29 14:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
In order to implement atomic mode sets, we'll need to hold state shared
by multiple crtcs in the drm_atomic_state struct. This patch moves
towards that goal by introducing struct intel_atomic_state for that
purpose and moving the staged pll configuration into it. Current state
will be moved in a follow up patch.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/intel_ddi.c | 11 ++--
drivers/gpu/drm/i915/intel_display.c | 104 +++++++++++++++--------------------
drivers/gpu/drm/i915/intel_drv.h | 8 ++-
4 files changed, 59 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b09173f..862edc4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -297,7 +297,6 @@ struct intel_shared_dpll_config {
struct intel_shared_dpll {
struct intel_shared_dpll_config config;
- struct intel_shared_dpll_config *new_config;
int active; /* count of number of active CRTCs (i.e. DPMS on) */
bool on; /* is the PLL actually active? Disabled during modeset */
@@ -504,6 +503,7 @@ struct drm_i915_error_state {
struct intel_connector;
struct intel_encoder;
struct intel_crtc_state;
+struct intel_atomic_state;
struct intel_initial_plane_config;
struct intel_crtc;
struct intel_limit;
@@ -546,6 +546,7 @@ struct drm_i915_display_funcs {
void (*get_initial_plane_config)(struct intel_crtc *,
struct intel_initial_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct drm_crtc *crtc);
void (*crtc_disable)(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ad8b73d..1cd541f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -909,6 +909,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
static bool
hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state,
struct intel_encoder *intel_encoder,
int clock)
@@ -926,7 +927,7 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
crtc_state->dpll_hw_state.wrpll = val;
- pll = intel_get_shared_dpll(intel_crtc, crtc_state);
+ pll = intel_get_shared_dpll(intel_crtc, state, crtc_state);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
pipe_name(intel_crtc->pipe));
@@ -1096,6 +1097,7 @@ found:
static bool
skl_ddi_pll_select(struct intel_crtc *intel_crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state,
struct intel_encoder *intel_encoder,
int clock)
@@ -1150,7 +1152,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
- pll = intel_get_shared_dpll(intel_crtc, crtc_state);
+ pll = intel_get_shared_dpll(intel_crtc, state, crtc_state);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
pipe_name(intel_crtc->pipe));
@@ -1171,6 +1173,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
* function should be folded into compute_config() eventually.
*/
bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = intel_crtc->base.dev;
@@ -1179,10 +1182,10 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
int clock = crtc_state->port_clock;
if (IS_SKYLAKE(dev))
- return skl_ddi_pll_select(intel_crtc, crtc_state,
+ return skl_ddi_pll_select(intel_crtc, state, crtc_state,
intel_encoder, clock);
else
- return hsw_ddi_pll_select(intel_crtc, crtc_state,
+ return hsw_ddi_pll_select(intel_crtc, state, crtc_state,
intel_encoder, clock);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3d220a6..159e6c8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3891,6 +3891,7 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
}
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
@@ -3905,7 +3906,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
crtc->base.base.id, pll->name);
- WARN_ON(pll->new_config->crtc_mask);
+ WARN_ON(state->shared_dpll[i].crtc_mask);
goto found;
}
@@ -3914,15 +3915,15 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
pll = &dev_priv->shared_dplls[i];
/* Only want to check enabled timings first */
- if (pll->new_config->crtc_mask == 0)
+ if (state->shared_dpll[i].crtc_mask == 0)
continue;
if (memcmp(&crtc_state->dpll_hw_state,
- &pll->new_config->hw_state,
- sizeof(pll->new_config->hw_state)) == 0) {
+ &state->shared_dpll[i].hw_state,
+ sizeof(state->shared_dpll[i].hw_state)) == 0) {
DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
crtc->base.base.id, pll->name,
- pll->new_config->crtc_mask,
+ state->shared_dpll[i].crtc_mask,
pll->active);
goto found;
}
@@ -3931,7 +3932,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
/* Ok no matching timings, maybe there's a free one? */
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
pll = &dev_priv->shared_dplls[i];
- if (pll->new_config->crtc_mask == 0) {
+ if (state->shared_dpll[i].crtc_mask == 0) {
DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
crtc->base.base.id, pll->name);
goto found;
@@ -3941,14 +3942,14 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
return NULL;
found:
- if (pll->new_config->crtc_mask == 0)
- pll->new_config->hw_state = crtc_state->dpll_hw_state;
+ if (state->shared_dpll[i].crtc_mask == 0)
+ state->shared_dpll[i].hw_state = crtc_state->dpll_hw_state;
crtc_state->shared_dpll = i;
DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
pipe_name(crtc->pipe));
- pll->new_config->crtc_mask |= 1 << crtc->pipe;
+ state->shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
return pll;
}
@@ -3962,6 +3963,7 @@ found:
* releasing the references of pipes specified in clear_pipes.
*/
static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
+ struct intel_atomic_state *state,
unsigned clear_pipes)
{
struct intel_shared_dpll *pll;
@@ -3970,54 +3972,23 @@ static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
pll = &dev_priv->shared_dplls[i];
- pll->new_config = kmemdup(&pll->config, sizeof pll->config,
- GFP_KERNEL);
- if (!pll->new_config)
- goto cleanup;
-
- pll->new_config->crtc_mask &= ~clear_pipes;
+ memcpy(&state->shared_dpll[i], &pll->config,
+ sizeof pll->config);
+ state->shared_dpll[i].crtc_mask &= ~clear_pipes;
}
return 0;
-
-cleanup:
- while (--i >= 0) {
- pll = &dev_priv->shared_dplls[i];
- kfree(pll->new_config);
- pll->new_config = NULL;
- }
-
- return -ENOMEM;
}
-static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
+static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv,
+ struct intel_atomic_state *state)
{
struct intel_shared_dpll *pll;
enum intel_dpll_id i;
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
pll = &dev_priv->shared_dplls[i];
-
- WARN_ON(pll->new_config == &pll->config);
-
- pll->config = *pll->new_config;
- kfree(pll->new_config);
- pll->new_config = NULL;
- }
-}
-
-static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
-{
- struct intel_shared_dpll *pll;
- enum intel_dpll_id i;
-
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- pll = &dev_priv->shared_dplls[i];
-
- WARN_ON(pll->new_config == &pll->config);
-
- kfree(pll->new_config);
- pll->new_config = NULL;
+ pll->config = state->shared_dpll[i];
}
}
@@ -6426,6 +6397,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
}
static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = crtc->base.dev;
@@ -7452,6 +7424,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
}
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = crtc->base.dev;
@@ -7498,7 +7471,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
else
crtc_state->dpll_hw_state.fp1 = fp;
- pll = intel_get_shared_dpll(crtc, crtc_state);
+ pll = intel_get_shared_dpll(crtc, state, crtc_state);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
pipe_name(crtc->pipe));
@@ -8070,9 +8043,10 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
}
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- if (!intel_ddi_pll_select(crtc, crtc_state))
+ if (!intel_ddi_pll_select(crtc, state, crtc_state))
return -EINVAL;
crtc->lowfreq_avail = false;
@@ -10417,14 +10391,15 @@ static bool intel_crtc_in_use(struct drm_crtc *crtc)
}
static void
-intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
+intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes,
+ struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder;
struct intel_crtc *intel_crtc;
struct drm_connector *connector;
- intel_shared_dpll_commit(dev_priv);
+ intel_shared_dpll_commit(dev_priv, state);
for_each_intel_encoder(dev, intel_encoder) {
if (!intel_encoder->base.crtc)
@@ -11022,6 +10997,7 @@ out:
}
static int __intel_set_mode_setup_plls(struct drm_device *dev,
+ struct intel_atomic_state *state,
unsigned modeset_pipes,
unsigned disable_pipes)
{
@@ -11033,21 +11009,18 @@ static int __intel_set_mode_setup_plls(struct drm_device *dev,
if (!dev_priv->display.crtc_compute_clock)
return 0;
- ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
+ ret = intel_shared_dpll_start_config(dev_priv, state, clear_pipes);
if (ret)
- goto done;
+ return ret;
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
- struct intel_crtc_state *state = intel_crtc->new_config;
+ struct intel_crtc_state *crtc_state = intel_crtc->new_config;
ret = dev_priv->display.crtc_compute_clock(intel_crtc,
- state);
- if (ret) {
- intel_shared_dpll_abort_config(dev_priv);
- goto done;
- }
+ state, crtc_state);
+ if (ret)
+ break;
}
-done:
return ret;
}
@@ -11063,6 +11036,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *saved_mode;
struct intel_crtc *intel_crtc;
+ struct intel_atomic_state *state = NULL;
int ret = 0;
saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
@@ -11088,7 +11062,14 @@ static int __intel_set_mode(struct drm_crtc *crtc,
prepare_pipes &= ~disable_pipes;
}
- ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
+ state = kzalloc(sizeof *state, GFP_KERNEL);
+ if (!state) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ ret = __intel_set_mode_setup_plls(dev, state,
+ modeset_pipes, disable_pipes);
if (ret)
goto done;
@@ -11124,7 +11105,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
/* Only after disabling all output pipelines that will be changed can we
* update the the output configuration. */
- intel_modeset_update_state(dev, prepare_pipes);
+ intel_modeset_update_state(dev, prepare_pipes, state);
modeset_update_crtc_power_domains(dev);
@@ -11155,6 +11136,7 @@ done:
if (ret && crtc->enabled)
crtc->mode = *saved_mode;
+ kfree(state);
kfree(saved_mode);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eef79cc..f2f4210 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -243,6 +243,10 @@ typedef struct dpll {
int p;
} intel_clock_t;
+struct intel_atomic_state {
+ struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
+};
+
struct intel_plane_state {
struct drm_plane_state base;
struct drm_rect src;
@@ -837,6 +841,7 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
bool intel_ddi_pll_select(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state);
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
@@ -962,7 +967,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
- struct intel_crtc_state *state);
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state);
void intel_put_shared_dpll(struct intel_crtc *crtc);
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
--
2.1.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] drm/i915: Move current pll config to shared global state
2015-01-29 14:55 [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode() Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 2/4] drm/i915: Move pll new_config field into intel_atomic_state Ander Conselvan de Oliveira
@ 2015-01-29 14:55 ` Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 4/4] drm/i915: Simplify pll state commit by swapping new and old state Ander Conselvan de Oliveira
2015-01-30 16:31 ` [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode() Daniel Vetter
3 siblings, 0 replies; 6+ messages in thread
From: Ander Conselvan de Oliveira @ 2015-01-29 14:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
This patch adds a display_state pointer to drm_i915_private and moves
the current pll config into it.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 15 ++++---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/intel_ddi.c | 13 ++++--
drivers/gpu/drm/i915/intel_display.c | 86 +++++++++++++++++++++++++-----------
4 files changed, 79 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3b332a4..eb18a99 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2765,17 +2765,20 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
drm_modeset_lock_all(dev);
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ struct intel_shared_dpll_config *pll_config;
+
+ pll_config = &dev_priv->display_state->shared_dpll[i];
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
- pll->config.crtc_mask, pll->active, yesno(pll->on));
+ pll_config->crtc_mask, pll->active, yesno(pll->on));
seq_printf(m, " tracked hardware state:\n");
- seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
+ seq_printf(m, " dpll: 0x%08x\n", pll_config->hw_state.dpll);
seq_printf(m, " dpll_md: 0x%08x\n",
- pll->config.hw_state.dpll_md);
- seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
- seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
- seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
+ pll_config->hw_state.dpll_md);
+ seq_printf(m, " fp0: 0x%08x\n", pll_config->hw_state.fp0);
+ seq_printf(m, " fp1: 0x%08x\n", pll_config->hw_state.fp1);
+ seq_printf(m, " wrpll: 0x%08x\n", pll_config->hw_state.wrpll);
}
drm_modeset_unlock_all(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 862edc4..132eb7b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -296,8 +296,6 @@ struct intel_shared_dpll_config {
};
struct intel_shared_dpll {
- struct intel_shared_dpll_config config;
-
int active; /* count of number of active CRTCs (i.e. DPMS on) */
bool on; /* is the PLL actually active? Disabled during modeset */
const char *name;
@@ -1784,6 +1782,8 @@ struct drm_i915_private {
struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif
+ struct intel_atomic_state *display_state;
+
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1cd541f..ff2197c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1747,7 +1747,10 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
+
+ I915_WRITE(WRPLL_CTL(pll->id), pll_config->hw_state.wrpll);
POSTING_READ(WRPLL_CTL(pll->id));
udelay(20);
}
@@ -1836,6 +1839,8 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
uint32_t val;
unsigned int dpll;
const struct skl_dpll_regs *regs = skl_dpll_regs;
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
dpll = pll->id + 1;
@@ -1844,13 +1849,13 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
DPLL_CRTL1_LINK_RATE_MASK(dpll));
- val |= pll->config.hw_state.ctrl1 << (dpll * 6);
+ val |= pll_config->hw_state.ctrl1 << (dpll * 6);
I915_WRITE(DPLL_CTRL1, val);
POSTING_READ(DPLL_CTRL1);
- I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
- I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
+ I915_WRITE(regs[pll->id].cfgcr1, pll_config->hw_state.cfgcr1);
+ I915_WRITE(regs[pll->id].cfgcr2, pll_config->hw_state.cfgcr2);
POSTING_READ(regs[pll->id].cfgcr1);
POSTING_READ(regs[pll->id].cfgcr2);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 159e6c8..fecffbb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1778,11 +1778,13 @@ static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
if (WARN_ON(pll == NULL))
return;
- WARN_ON(!pll->config.crtc_mask);
+ WARN_ON(!pll_config->crtc_mask);
if (pll->active == 0) {
DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
WARN_ON(pll->on);
@@ -1805,11 +1807,13 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
if (WARN_ON(pll == NULL))
return;
- if (WARN_ON(pll->config.crtc_mask == 0))
+ if (WARN_ON(pll_config->crtc_mask == 0))
return;
DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
@@ -1835,13 +1839,15 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
/* PCH only available on ILK+ */
BUG_ON(INTEL_INFO(dev)->gen < 5);
if (WARN_ON(pll == NULL))
return;
- if (WARN_ON(pll->config.crtc_mask == 0))
+ if (WARN_ON(pll_config->crtc_mask == 0))
return;
DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
@@ -3871,18 +3877,21 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
void intel_put_shared_dpll(struct intel_crtc *crtc)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
if (pll == NULL)
return;
- if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
+ if (!(pll_config->crtc_mask & (1 << crtc->pipe))) {
WARN(1, "bad %s crtc mask\n", pll->name);
return;
}
- pll->config.crtc_mask &= ~(1 << crtc->pipe);
- if (pll->config.crtc_mask == 0) {
+ pll_config->crtc_mask &= ~(1 << crtc->pipe);
+ if (pll_config->crtc_mask == 0) {
WARN_ON(pll->on);
WARN_ON(pll->active);
}
@@ -3966,14 +3975,16 @@ static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
struct intel_atomic_state *state,
unsigned clear_pipes)
{
- struct intel_shared_dpll *pll;
+ struct intel_shared_dpll_config *pll_config;
enum intel_dpll_id i;
+ /* FIXME: convert this to a simple memdup */
+
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- pll = &dev_priv->shared_dplls[i];
+ pll_config = &dev_priv->display_state->shared_dpll[i];
- memcpy(&state->shared_dpll[i], &pll->config,
- sizeof pll->config);
+ memcpy(&state->shared_dpll[i], pll_config,
+ sizeof *pll_config);
state->shared_dpll[i].crtc_mask &= ~clear_pipes;
}
@@ -3983,12 +3994,14 @@ static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv,
struct intel_atomic_state *state)
{
- struct intel_shared_dpll *pll;
+ struct intel_shared_dpll_config *pll_config;
enum intel_dpll_id i;
+ /* FIXME: convert this to a poiner swap */
+
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- pll = &dev_priv->shared_dplls[i];
- pll->config = state->shared_dpll[i];
+ pll_config = &dev_priv->display_state->shared_dpll[i];
+ *pll_config = state->shared_dpll[i];
}
}
@@ -10864,6 +10877,8 @@ check_shared_dpll_state(struct drm_device *dev)
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
int enabled_crtcs = 0, active_crtcs = 0;
bool active;
@@ -10873,9 +10888,9 @@ check_shared_dpll_state(struct drm_device *dev)
active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
- I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
+ I915_STATE_WARN(pll->active > hweight32(pll_config->crtc_mask),
"more active pll users than references: %i vs %i\n",
- pll->active, hweight32(pll->config.crtc_mask));
+ pll->active, hweight32(pll_config->crtc_mask));
I915_STATE_WARN(pll->active && !pll->on,
"pll in active use but not on in sw tracking\n");
I915_STATE_WARN(pll->on && !pll->active,
@@ -10893,11 +10908,11 @@ check_shared_dpll_state(struct drm_device *dev)
I915_STATE_WARN(pll->active != active_crtcs,
"pll active crtcs mismatch (expected %i, found %i)\n",
pll->active, active_crtcs);
- I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
+ I915_STATE_WARN(hweight32(pll_config->crtc_mask) != enabled_crtcs,
"pll enabled crtcs mismatch (expected %i, found %i)\n",
- hweight32(pll->config.crtc_mask), enabled_crtcs);
+ hweight32(pll_config->crtc_mask), enabled_crtcs);
- I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
+ I915_STATE_WARN(pll->on && memcmp(&pll_config->hw_state, &dpll_hw_state,
sizeof(dpll_hw_state)),
"pll hw state mismatch\n");
}
@@ -11675,17 +11690,23 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
- I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
+
+ I915_WRITE(PCH_FP0(pll->id), pll_config->hw_state.fp0);
+ I915_WRITE(PCH_FP1(pll->id), pll_config->hw_state.fp1);
}
static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
+
/* PCH refclock must be enabled first */
ibx_assert_pch_refclk_enabled(dev_priv);
- I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
+ I915_WRITE(PCH_DPLL(pll->id), pll_config->hw_state.dpll);
/* Wait for the clocks to stabilize. */
POSTING_READ(PCH_DPLL(pll->id));
@@ -11696,7 +11717,7 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
*
* So write it again.
*/
- I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
+ I915_WRITE(PCH_DPLL(pll->id), pll_config->hw_state.dpll);
POSTING_READ(PCH_DPLL(pll->id));
udelay(200);
}
@@ -13139,6 +13160,13 @@ void intel_modeset_init(struct drm_device *dev)
enum pipe pipe;
struct intel_crtc *crtc;
+ dev_priv->display_state = kzalloc(sizeof *dev_priv->display_state,
+ GFP_KERNEL);
+ if (!dev_priv->display_state) {
+ DRM_DEBUG_KMS("Failed to allocate display state.\n");
+ return;
+ }
+
drm_mode_config_init(dev);
dev->mode_config.min_width = 0;
@@ -13509,22 +13537,24 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+ struct intel_shared_dpll_config *pll_config =
+ &dev_priv->display_state->shared_dpll[pll->id];
pll->on = pll->get_hw_state(dev_priv, pll,
- &pll->config.hw_state);
+ &pll_config->hw_state);
pll->active = 0;
- pll->config.crtc_mask = 0;
+ pll_config->crtc_mask = 0;
for_each_intel_crtc(dev, crtc) {
if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
pll->active++;
- pll->config.crtc_mask |= 1 << crtc->pipe;
+ pll_config->crtc_mask |= 1 << crtc->pipe;
}
}
DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
- pll->name, pll->config.crtc_mask, pll->on);
+ pll->name, pll_config->crtc_mask, pll->on);
- if (pll->config.crtc_mask)
+ if (pll_config->crtc_mask)
intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
}
@@ -13749,6 +13779,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
mutex_lock(&dev->struct_mutex);
intel_cleanup_gt_powersave(dev);
mutex_unlock(&dev->struct_mutex);
+
+ kfree(dev_priv->display_state);
}
/*
--
2.1.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] drm/i915: Simplify pll state commit by swapping new and old state
2015-01-29 14:55 [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode() Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 2/4] drm/i915: Move pll new_config field into intel_atomic_state Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 3/4] drm/i915: Move current pll config to shared global state Ander Conselvan de Oliveira
@ 2015-01-29 14:55 ` Ander Conselvan de Oliveira
2015-01-31 21:37 ` shuang.he
2015-01-30 16:31 ` [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode() Daniel Vetter
3 siblings, 1 reply; 6+ messages in thread
From: Ander Conselvan de Oliveira @ 2015-01-29 14:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
This deletes some code and is closer to what the logic will look like
with atomic mode setting.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 58 ++++++++----------------------------
1 file changed, 12 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fecffbb..96176c1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3963,46 +3963,11 @@ found:
return pll;
}
-/**
- * intel_shared_dpll_start_config - start a new PLL staged config
- * @dev_priv: DRM device
- * @clear_pipes: mask of pipes that will have their PLLs freed
- *
- * Starts a new PLL staged config, copying the current config but
- * releasing the references of pipes specified in clear_pipes.
- */
-static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
- struct intel_atomic_state *state,
- unsigned clear_pipes)
-{
- struct intel_shared_dpll_config *pll_config;
- enum intel_dpll_id i;
-
- /* FIXME: convert this to a simple memdup */
-
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- pll_config = &dev_priv->display_state->shared_dpll[i];
-
- memcpy(&state->shared_dpll[i], pll_config,
- sizeof *pll_config);
- state->shared_dpll[i].crtc_mask &= ~clear_pipes;
- }
-
- return 0;
-}
-
-static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv,
- struct intel_atomic_state *state)
+static struct intel_atomic_state *
+intel_atomic_state_duplicate(struct drm_i915_private *dev_priv)
{
- struct intel_shared_dpll_config *pll_config;
- enum intel_dpll_id i;
-
- /* FIXME: convert this to a poiner swap */
-
- for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- pll_config = &dev_priv->display_state->shared_dpll[i];
- *pll_config = state->shared_dpll[i];
- }
+ return kmemdup(dev_priv->display_state,
+ sizeof *dev_priv->display_state, GFP_KERNEL);
}
static void cpt_verify_modeset(struct drm_device *dev, int pipe)
@@ -10405,14 +10370,15 @@ static bool intel_crtc_in_use(struct drm_crtc *crtc)
static void
intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes,
- struct intel_atomic_state *state)
+ struct intel_atomic_state **state)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder;
struct intel_crtc *intel_crtc;
struct drm_connector *connector;
- intel_shared_dpll_commit(dev_priv, state);
+ /* Commit PLL and other global state */
+ swap(dev_priv->display_state, *state);
for_each_intel_encoder(dev, intel_encoder) {
if (!intel_encoder->base.crtc)
@@ -11020,13 +10986,13 @@ static int __intel_set_mode_setup_plls(struct drm_device *dev,
unsigned clear_pipes = modeset_pipes | disable_pipes;
struct intel_crtc *intel_crtc;
int ret = 0;
+ int i;
if (!dev_priv->display.crtc_compute_clock)
return 0;
- ret = intel_shared_dpll_start_config(dev_priv, state, clear_pipes);
- if (ret)
- return ret;
+ for (i = 0; i < dev_priv->num_shared_dpll; i++)
+ state->shared_dpll[i].crtc_mask &= ~clear_pipes;
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
struct intel_crtc_state *crtc_state = intel_crtc->new_config;
@@ -11077,7 +11043,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
prepare_pipes &= ~disable_pipes;
}
- state = kzalloc(sizeof *state, GFP_KERNEL);
+ state = intel_atomic_state_duplicate(dev_priv);
if (!state) {
ret = -ENOMEM;
goto done;
@@ -11120,7 +11086,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
/* Only after disabling all output pipelines that will be changed can we
* update the the output configuration. */
- intel_modeset_update_state(dev, prepare_pipes, state);
+ intel_modeset_update_state(dev, prepare_pipes, &state);
modeset_update_crtc_power_domains(dev);
--
2.1.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode()
2015-01-29 14:55 [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode() Ander Conselvan de Oliveira
` (2 preceding siblings ...)
2015-01-29 14:55 ` [PATCH 4/4] drm/i915: Simplify pll state commit by swapping new and old state Ander Conselvan de Oliveira
@ 2015-01-30 16:31 ` Daniel Vetter
3 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2015-01-30 16:31 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
On Thu, Jan 29, 2015 at 04:55:08PM +0200, Ander Conselvan de Oliveira wrote:
> This simplifies __intel_set_mode() a little.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Merged this one here, please sign up Matt or someone else suitable for the
in-depth review.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++------------
> 1 file changed, 33 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 423ef95..3d220a6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11021,6 +11021,36 @@ out:
> return pipe_config;
> }
>
> +static int __intel_set_mode_setup_plls(struct drm_device *dev,
> + unsigned modeset_pipes,
> + unsigned disable_pipes)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + unsigned clear_pipes = modeset_pipes | disable_pipes;
> + struct intel_crtc *intel_crtc;
> + int ret = 0;
> +
> + if (!dev_priv->display.crtc_compute_clock)
> + return 0;
> +
> + ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
> + if (ret)
> + goto done;
> +
> + for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
> + struct intel_crtc_state *state = intel_crtc->new_config;
> + ret = dev_priv->display.crtc_compute_clock(intel_crtc,
> + state);
> + if (ret) {
> + intel_shared_dpll_abort_config(dev_priv);
> + goto done;
> + }
> + }
> +
> +done:
> + return ret;
> +}
> +
> static int __intel_set_mode(struct drm_crtc *crtc,
> struct drm_display_mode *mode,
> int x, int y, struct drm_framebuffer *fb,
> @@ -11058,23 +11088,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> prepare_pipes &= ~disable_pipes;
> }
>
> - if (dev_priv->display.crtc_compute_clock) {
> - unsigned clear_pipes = modeset_pipes | disable_pipes;
> -
> - ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
> - if (ret)
> - goto done;
> -
> - for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
> - struct intel_crtc_state *state = intel_crtc->new_config;
> - ret = dev_priv->display.crtc_compute_clock(intel_crtc,
> - state);
> - if (ret) {
> - intel_shared_dpll_abort_config(dev_priv);
> - goto done;
> - }
> - }
> - }
> + ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
> + if (ret)
> + goto done;
>
> for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
> intel_crtc_disable(&intel_crtc->base);
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 4/4] drm/i915: Simplify pll state commit by swapping new and old state
2015-01-29 14:55 ` [PATCH 4/4] drm/i915: Simplify pll state commit by swapping new and old state Ander Conselvan de Oliveira
@ 2015-01-31 21:37 ` shuang.he
0 siblings, 0 replies; 6+ messages in thread
From: shuang.he @ 2015-01-31 21:37 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, ander.conselvan.de.oliveira
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5683
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 353/353 353/353
ILK 353/353 353/353
SNB 400/422 400/422
IVB +1 485/487 486/487
BYT 296/296 296/296
HSW +1-11 404/405 394/405
BDW -1 401/402 400/402
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M21)
*HSW igt_gem_pwrite_pread_display-copy-performance PASS(5, M40M20) DMESG_WARN(1, M40)
HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M40)PASS(18, M40M20) PASS(1, M40)
*HSW igt_kms_cursor_crc_cursor-size-change PASS(2, M40) TIMEOUT(1, M40)
*HSW igt_kms_fence_pin_leak PASS(2, M40) TIMEOUT(1, M40)
*HSW igt_kms_flip_bo-too-big PASS(2, M40) TIMEOUT(1, M40)
*HSW igt_kms_flip_bo-too-big-interruptible PASS(2, M40) CRASH(1, M40)
*HSW igt_kms_flip_dpms-vs-vblank-race PASS(2, M40) TIMEOUT(1, M40)
*HSW igt_kms_flip_event_leak PASS(2, M40) TIMEOUT(1, M40)
*HSW igt_kms_flip_flip-vs-dpms-off-vs-modeset PASS(2, M40) TIMEOUT(1, M40)
*HSW igt_kms_flip_flip-vs-expired-vblank PASS(2, M40) TIMEOUT(1, M40)
*HSW igt_kms_flip_flip-vs-expired-vblank-interruptible PASS(2, M40) CRASH(1, M40)
*HSW igt_kms_flip_nonexisting-fb PASS(3, M40M20) TIMEOUT(1, M40)
*BDW igt_kms_fence_pin_leak PASS(2, M30) TIMEOUT(1, M30)
Note: You need to pay more attention to line start with '*'
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2015-01-29 14:55 [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode() Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 2/4] drm/i915: Move pll new_config field into intel_atomic_state Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 3/4] drm/i915: Move current pll config to shared global state Ander Conselvan de Oliveira
2015-01-29 14:55 ` [PATCH 4/4] drm/i915: Simplify pll state commit by swapping new and old state Ander Conselvan de Oliveira
2015-01-31 21:37 ` shuang.he
2015-01-30 16:31 ` [PATCH 1/4] drm/i915: Split shared dpll setup out of __intel_set_mode() Daniel Vetter
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