From: Damien Lespiau <damien.lespiau@intel.com>
To: Nick Hoath <nicholas.hoath@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] gen 9 h/w w/a (WaClearFlowControlGpgpuContextSave)
Date: Wed, 18 Feb 2015 18:48:11 +0000 [thread overview]
Message-ID: <20150218184810.GG7298@strange.ger.corp.intel.com> (raw)
In-Reply-To: <1424272568-5920-4-git-send-email-nicholas.hoath@intel.com>
On Wed, Feb 18, 2015 at 03:16:08PM +0000, Nick Hoath wrote:
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Can you please prefix subjects by drm/i915/skl or drm/i915/gen9? that
helps people doing selective backports. In any case, we at least use
drm/i915 as prefixes, not empty like here :).
While you're enabling the write to SP here, are the second part of the
W/A (setting it to 0) done in the shader? As always the
documentation/bug report are very thin...
--
Damien
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7f9150b..0326399 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6216,6 +6216,7 @@ enum skl_disp_power_wells {
> #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
>
> #define GEN8_ROW_CHICKEN 0xe4f0
> +#define ENABLE_FLOW_CONTROL_WRITES (1<<15)
> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
> #define STALL_DOP_GATING_DISABLE (1<<5)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2060610..36df3d4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -950,7 +950,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> /* WaDisablePartialInstShootdown:skl */
> + /* WaClearFlowControlGpgpuContextSave:skl */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> + ENABLE_FLOW_CONTROL_WRITES |
> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>
> /* Syncing dependencies between camera and graphics */
> --
> 2.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2015-02-18 18:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-18 15:16 [PATCH 0/3] drm/i915: Further Skylake h/w w/a's Nick Hoath
2015-02-18 15:16 ` [PATCH 1/3] drm/i915: gen 9 h/w w/a (Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset) Nick Hoath
2015-02-18 18:19 ` Damien Lespiau
2015-02-23 23:34 ` Daniel Vetter
2015-02-18 15:16 ` [PATCH 2/3] drm/i915: gen 9 h/w w/a (WaDisablePooledEuLoadBalancingFix) Nick Hoath
2015-02-18 18:49 ` Damien Lespiau
2015-02-18 15:16 ` [PATCH 3/3] gen 9 h/w w/a (WaClearFlowControlGpgpuContextSave) Nick Hoath
2015-02-18 18:48 ` Damien Lespiau [this message]
2015-02-23 23:36 ` Daniel Vetter
2015-02-18 22:24 ` shuang.he
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