From: Daniel Vetter <daniel@ffwll.ch>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] gen 9 h/w w/a (WaClearFlowControlGpgpuContextSave)
Date: Tue, 24 Feb 2015 00:36:26 +0100 [thread overview]
Message-ID: <20150223233626.GY24485@phenom.ffwll.local> (raw)
In-Reply-To: <20150218184810.GG7298@strange.ger.corp.intel.com>
On Wed, Feb 18, 2015 at 06:48:11PM +0000, Damien Lespiau wrote:
> On Wed, Feb 18, 2015 at 03:16:08PM +0000, Nick Hoath wrote:
> > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
>
> Can you please prefix subjects by drm/i915/skl or drm/i915/gen9? that
> helps people doing selective backports. In any case, we at least use
> drm/i915 as prefixes, not empty like here :).
>
> While you're enabling the write to SP here, are the second part of the
> W/A (setting it to 0) done in the shader? As always the
> documentation/bug report are very thin...
If there's a part to be done in shaders we need to audit rendercpy, mesa,
libva, ddx and everything else too ... Please cc relevant
lists/maintainers for the next iteration.
Thanks, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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next prev parent reply other threads:[~2015-02-23 23:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-18 15:16 [PATCH 0/3] drm/i915: Further Skylake h/w w/a's Nick Hoath
2015-02-18 15:16 ` [PATCH 1/3] drm/i915: gen 9 h/w w/a (Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset) Nick Hoath
2015-02-18 18:19 ` Damien Lespiau
2015-02-23 23:34 ` Daniel Vetter
2015-02-18 15:16 ` [PATCH 2/3] drm/i915: gen 9 h/w w/a (WaDisablePooledEuLoadBalancingFix) Nick Hoath
2015-02-18 18:49 ` Damien Lespiau
2015-02-18 15:16 ` [PATCH 3/3] gen 9 h/w w/a (WaClearFlowControlGpgpuContextSave) Nick Hoath
2015-02-18 18:48 ` Damien Lespiau
2015-02-23 23:36 ` Daniel Vetter [this message]
2015-02-18 22:24 ` shuang.he
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