From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()
Date: Mon, 2 Mar 2015 16:49:31 +0200 [thread overview]
Message-ID: <20150302144931.GY11371@intel.com> (raw)
In-Reply-To: <20150302144458.GY24485@phenom.ffwll.local>
On Mon, Mar 02, 2015 at 03:44:58PM +0100, Daniel Vetter wrote:
> On Fri, Feb 27, 2015 at 08:09:20PM +0200, Ville Syrjälä wrote:
> > On Fri, Feb 27, 2015 at 09:57:20AM -0800, Jesse Barnes wrote:
> > > On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Now that we have drm_planes for the cursor and primary we can move the
> > > > pixel_size handling into vlv_compute_drain_latency() and just pass the
> > > > appropriate plane to it.
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++-------------------------
> > > > 1 file changed, 16 insertions(+), 26 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 5515d10..fffcf64 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -727,16 +727,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
> > > > }
> > > >
> > > > static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
> > > > - int pixel_size)
> > > > + struct drm_plane *plane)
> > > > {
> > > > struct drm_device *dev = crtc->dev;
> > > > - int entries, prec_mult, drain_latency;
> > > > - int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
> > > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > > + int entries, prec_mult, drain_latency, pixel_size;
> > > > + int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
> > > > const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
> > > >
> > > > + /*
> > > > + * FIXME the plane might have an fb
> > > > + * but be invisible (eg. due to clipping)
> > > > + */
> > > > + if (!intel_crtc->active || !plane->fb)
> > > > + return 0;
> > > > +
> > > > if (WARN(clock == 0, "Pixel clock is zero!\n"))
> > > > return 0;
> > > >
> > > > + pixel_size = drm_format_plane_cpp(plane->fb->pixel_format, 0);
> > > > +
> > > > if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
> > > > return 0;
> > > >
> > > > @@ -770,31 +780,11 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
> > > > struct drm_device *dev = crtc->dev;
> > > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > > - int pixel_size;
> > > > enum pipe pipe = intel_crtc->pipe;
> > > > struct vlv_wm_values wm = dev_priv->wm.vlv;
> > > >
> > > > - wm.ddl[pipe].primary = 0;
> > > > - wm.ddl[pipe].cursor = 0;
> > > > -
> > > > - if (!intel_crtc_active(crtc)) {
> > > > - vlv_write_wm_values(intel_crtc, &wm);
> > > > - return;
> > > > - }
> > > > -
> > > > - /* Primary plane Drain Latency */
> > > > - pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
> > > > - wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
> > > > -
> > > > - /* Cursor Drain Latency
> > > > - * BPP is always 4 for cursor
> > > > - */
> > > > - pixel_size = 4;
> > > > -
> > > > - /* Program cursor DL only if it is enabled */
> > > > - if (intel_crtc->cursor_base)
> > > > - wm.ddl[pipe].cursor =
> > > > - vlv_compute_drain_latency(crtc, pixel_size);
> > > > + wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
> > > > + wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
> > > >
> > > > vlv_write_wm_values(intel_crtc, &wm);
> > > > }
> > > > @@ -961,7 +951,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
> > > >
> > > > if (enabled)
> > > > wm.ddl[pipe].sprite[sprite] =
> > > > - vlv_compute_drain_latency(crtc, pixel_size);
> > > > + vlv_compute_drain_latency(crtc, plane);
> > > > else
> > > > wm.ddl[pipe].sprite[sprite] = 0;
> > > >
> > > >
> > >
> > > Nice.
> >
> > Actually this is going to have issues now that atomic is partially in.
> > We'd need to look at plane->state->fb now, but that steps on the same
> > turf as Matt's latest patches.
>
> All the wm computation needs to be moved over to look at plane states, not
> plane->state - we need to do all this in the check phase when state
> objects haven't been commited yet. Which is a lot more work and probably
> best done separately in one go than all over the place and inconsistently.
Sure, but the quick "keep things sort of working" fix is to look at
plane->state since we currently do the wm calculation from commit.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-03-02 14:49 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-10 13:28 [PATCH 00/12] drm/i915: Redo VLV/CHV watermark code ville.syrjala
2015-02-10 13:28 ` [PATCH 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8 ville.syrjala
2015-02-27 17:36 ` Jesse Barnes
2015-02-27 18:02 ` Ville Syrjälä
[not found] ` <54F42A58.1020103@linux.intel.com>
2015-03-02 9:36 ` Arun R Murthy
2015-02-10 13:28 ` [PATCH 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines ville.syrjala
2015-02-27 17:38 ` Jesse Barnes
2015-02-27 18:06 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 03/12] drm/i915: Simplify VLV drain latency computation ville.syrjala
2015-02-27 17:40 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 04/12] drm/i915: Hide VLV DDL precision handling ville.syrjala
2015-02-27 17:46 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 05/12] drm/i915: Reorganize VLV DDL setup ville.syrjala
2015-02-27 17:52 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency() ville.syrjala
2015-02-27 17:57 ` Jesse Barnes
2015-02-27 18:09 ` Ville Syrjälä
2015-02-27 20:37 ` Jesse Barnes
2015-03-02 14:44 ` Daniel Vetter
2015-03-02 14:49 ` Ville Syrjälä [this message]
2015-03-02 17:18 ` Daniel Vetter
2015-02-10 13:28 ` [PATCH 07/12] drm/i915: Read out display FIFO size on VLV/CHV ville.syrjala
2015-02-12 18:59 ` [PATCH v2 " ville.syrjala
2015-02-27 18:04 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled " ville.syrjala
2015-02-27 20:38 ` Jesse Barnes
2015-02-27 20:48 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 09/12] drm/i915: Rewrite VLV/CHV watermark code ville.syrjala
2015-03-05 17:22 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 10/12] drm/i915: Support maxfifo with two planes on CHV ville.syrjala
2015-03-04 14:04 ` Purushothaman, Vijay A
2015-03-04 14:50 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 11/12] drm/i915: Program PFI credits for VLV ville.syrjala
2015-03-04 14:25 ` Purushothaman, Vijay A
2015-03-04 15:06 ` Ville Syrjälä
2015-03-04 15:26 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV ville.syrjala
2015-02-11 0:01 ` shuang.he
2015-02-26 19:01 ` [PATCH v2 " ville.syrjala
2015-03-04 14:28 ` [PATCH " Purushothaman, Vijay A
2015-03-04 15:07 ` Ville Syrjälä
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150302144931.GY11371@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=daniel@ffwll.ch \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox