Re: i915 driver doesn't find all Modelines that nouveau driver finds

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Mar 02, 2015 at 07:07:47PM +0100, Daniel Vetter wrote:
> On Mon, Mar 02, 2015 at 11:33:39AM -0500, Brian J. Murrell wrote:
> > On Mon, 2015-03-02 at 09:07 +0000, Chris Wilson wrote:
> > 
> > > Can you please attach dmesg with drm.debug=6 on the command line?
> > 
> > Please find it attached.  I did notice in it though:
> > 
> > [   50.508381] [drm:drm_mode_debug_printmodeline] Modeline 27:"1600x1200" 0 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
> > [   50.508383] [drm:drm_mode_prune_invalid] Not using 1600x1200 mode 15
> > [   50.508385] [drm:drm_mode_debug_printmodeline] Modeline 28:"1600x1200" 0 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
> > [   50.508385] [drm:drm_mode_prune_invalid] Not using 1600x1200 mode 15
> > [   50.508387] [drm:drm_mode_debug_printmodeline] Modeline 66:"1400x1050" 0 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
> > [   50.508388] [drm:drm_mode_prune_invalid] Not using 1400x1050 mode 15
> > [   50.508390] [drm:drm_mode_debug_printmodeline] Modeline 71:"1600x1200" 0 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
> > [   50.508390] [drm:drm_mode_prune_invalid] Not using 1600x1200 mode 15
> > 
> > Why would it think those modes are invalid?
> 
> 15 = dotclock too high for your chip.

The <180MHz modes are dropped only due to the +5% we add to account for SSC on
FDI. I wonder if we really need that much?

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ca49b6f..2df5a9a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7370,9 +7370,9 @@ int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
 	/*
 	 * Account for spread spectrum to avoid
 	 * oversubscribing the link. Max center spread
-	 * is 2.5%; use 5% for safety's sake.
+	 * is 2.5%.
 	 */
-	u32 bps = target_clock * bpp * 21 / 20;
+	u32 bps = target_clock * bpp * 41 / 40;
 	return DIV_ROUND_UP(bps, link_bw * 8);
 }

would at least allow the 175.5MHz mode through while dropping the other ones.

-- 
Ville Syrjälä
Intel OTC
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