Re: [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 intermediate frequencies

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Sonika Jindal <sonika.jindal@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 intermediate frequencies
Date: Wed, 4 Mar 2015 13:25:11 +0200	[thread overview]
Message-ID: <20150304112511.GN11371@intel.com> (raw)
In-Reply-To: <1424497333-1393-5-git-send-email-sonika.jindal@intel.com>

On Sat, Feb 21, 2015 at 11:12:13AM +0530, Sonika Jindal wrote:
> v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
> (Ville)
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c |   28 ++++++++++++++++++++++------
>  1 file changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cf7a0f5..62bc6c1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1079,7 +1079,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
>  }
>  
>  static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
> +skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>  {
>  	u32 ctrl1;
>  
> @@ -1088,19 +1088,35 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
>  	pipe_config->dpll_hw_state.cfgcr2 = 0;
>  
>  	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
> -	switch (link_bw) {
> -	case DP_LINK_BW_1_62:
> +	switch (link_clock / 2) {
> +	case 81000:
>  		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
>  					      SKL_DPLL0);
>  		break;
> -	case DP_LINK_BW_2_7:
> +	case 135000:
>  		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
>  					      SKL_DPLL0);
>  		break;
> -	case DP_LINK_BW_5_4:
> +	case 270000:
>  		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
>  					      SKL_DPLL0);
>  		break;
> +	case 162000:
> +		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
> +					      SKL_DPLL0);
> +		break;
> +	/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
> +	results in CDCLK change. Need to handle the change of CDCLK by
> +	disabling pipes and re-enabling them */
> +	case 108000:
> +		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
> +					      SKL_DPLL0);
> +		break;
> +	case 216000:
> +		ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
> +					      SKL_DPLL0);
> +		break;
> +
>  	}
>  	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
>  }
> @@ -1395,7 +1411,7 @@ found:
>  	}
>  
>  	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
> -		skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
> +		skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
>  	else
> -- 
> 1.7.10.4

-- 
Ville Syrjälä
Intel OTC
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