[PATCH v3 00/10] Added missing changes for Turbo feature on SKL

[PATCH v3 00/10] Added missing changes for Turbo feature on SKL

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

This patch series adds the missing changes, required for proper functioning
of the Turbo feature on SKL.
Most of the changes are mainly due to the fact that on SKL, the frequency has 
to be programmed in units of 16.66 MHZ and the time period value programmed 
in Up/Down EI & threshold registers, is in units of 1.333 micro seconds.
In this version, based on Ville & Damien's suggestions, have reworked 
the patches to store the frequency values inside the dev_priv->rps in 
the original hardware units for SKL. This helped to avoid all the special 
cases during normal codepaths, limiting them to init and one debugfs function.

Akash Goel (10):
  drm/i915/skl: Added new macros
  drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()
  drm/i915/skl: Updated the gen6_init_rps_frequencies function
  drm/i915/skl: Updated the gen6_set_rps function
  drm/i915/skl: Restructured the gen6_set_rps_thresholds function
  drm/i915/skl: Updated the gen6_rps_limits function
  drm/i915/skl: Updated the gen9_enable_rps function
  drm/i915/skl: Updated the i915_frequency_info debugfs function
  drm/i915/skl: Updated the act_freq_mhz_show sysfs function
  drm/i915/skl: Enabling processing of Turbo interrupts

 drivers/gpu/drm/i915/i915_debugfs.c |  25 ++++---
 drivers/gpu/drm/i915/i915_drv.h     |   1 +
 drivers/gpu/drm/i915/i915_irq.c     |   5 --
 drivers/gpu/drm/i915/i915_reg.h     |   9 +++
 drivers/gpu/drm/i915/i915_sysfs.c   |   4 +-
 drivers/gpu/drm/i915/intel_pm.c     | 129 ++++++++++++++++++++----------------
 6 files changed, 102 insertions(+), 71 deletions(-)

-- 
1.9.2

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[PATCH 1/8] drm/i915/skl: Added new macros

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
have changed slightly. Also on SKL, frequency is specified in
units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
platforms and the time values are expressed in units of 1.33 us,
compared to 1.28 us for earlier platforms.
Added new macros for the aforementioned changes.

v2: Renamed the GT_FREQ_FROM_PERIOD macro to GT_INTERVAL_FROM_US (Damien)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d42040f..73b49d5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2523,6 +2523,7 @@ struct drm_i915_cmd_table {
 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
 
 #define GT_FREQUENCY_MULTIPLIER 50
+#define GEN9_FREQ_SCALER 3
 
 #include "i915_trace.h"
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..278b7be 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2427,6 +2427,12 @@ enum skl_disp_power_wells {
 #define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
 #define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
 
+#define INTERVAL_1_28_US(us)	(((us) * 100) >> 7)
+#define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
+#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
+				INTERVAL_1_33_US(us) : \
+				INTERVAL_1_28_US(us))
+
 /*
  * Logical Context regs
  */
@@ -6080,6 +6086,7 @@ enum skl_disp_power_wells {
 #define   GEN6_TURBO_DISABLE			(1<<31)
 #define   GEN6_FREQUENCY(x)			((x)<<25)
 #define   HSW_FREQUENCY(x)			((x)<<24)
+#define   GEN9_FREQUENCY(x)			((x)<<23)
 #define   GEN6_OFFSET(x)			((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
 #define GEN6_RC_VIDEO_FREQ			0xA00C
@@ -6098,8 +6105,10 @@ enum skl_disp_power_wells {
 #define GEN6_RPSTAT1				0xA01C
 #define   GEN6_CAGF_SHIFT			8
 #define   HSW_CAGF_SHIFT			7
+#define   GEN9_CAGF_SHIFT			23
 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
+#define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
 #define GEN6_RP_CONTROL				0xA024
 #define   GEN6_RP_MEDIA_TURBO			(1<<11)
 #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
-- 
1.9.2

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[PATCH 2/8] drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, frequency is specified in units of 16.66 MHZ.
Updated the intel_gpu_freq() and intel_freq_opecode() functions
to do the conversion appropriately.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7dcb5b6..1b36d0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6660,7 +6660,9 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
-	if (IS_CHERRYVIEW(dev_priv->dev))
+	if (IS_GEN9(dev_priv->dev))
+		return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
+	else if (IS_CHERRYVIEW(dev_priv->dev))
 		return chv_gpu_freq(dev_priv, val);
 	else if (IS_VALLEYVIEW(dev_priv->dev))
 		return byt_gpu_freq(dev_priv, val);
@@ -6670,7 +6672,9 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
-	if (IS_CHERRYVIEW(dev_priv->dev))
+	if (IS_GEN9(dev_priv->dev))
+		return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
+	else if (IS_CHERRYVIEW(dev_priv->dev))
 		return chv_freq_opcode(dev_priv, val);
 	else if (IS_VALLEYVIEW(dev_priv->dev))
 		return byt_freq_opcode(dev_priv, val);
-- 
1.9.2

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[PATCH 3/8] drm/i915/skl: Updated the gen6_init_rps_frequencies function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
function for SKL, to store the frequency values as per the actual hardware unit.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1b36d0e..9dcfca6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4032,6 +4032,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
 	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
 	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
 	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
+	if (IS_SKYLAKE(dev)) {
+		/* Store the frequency values in 16.66 MHZ units, which is
+		   the natural hardware unit for SKL */
+		dev_priv->rps.rp0_freq /= GEN9_FREQ_SCALER;
+		dev_priv->rps.rp1_freq /= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq /= GEN9_FREQ_SCALER;
+	}
 	/* hw_max = RP0 until we check for overclocking */
 	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
 
-- 
1.9.2

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[PATCH 4/8] drm/i915/skl: Updated the gen6_set_rps function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, the frequency is programmed differently in RPNSWREQ (A008)
register (from bits 23 to 31, compared to bits 24 to 31). So updated
the gen6_set_rps function, as per this change.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9dcfca6..339a034 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3798,7 +3798,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		if (IS_GEN9(dev))
+			I915_WRITE(GEN6_RPNSWREQ,
+				   GEN9_FREQUENCY(val));
+		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   HSW_FREQUENCY(val));
 		else
-- 
1.9.2

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[PATCH 5/8] drm/i915/skl: Restructured the gen6_set_rps_thresholds function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Prior to SKL, the time period programmed in Up/Down EI & Up/Down
threshold registers was in units of 1.28 micro seconds. But for
SKL, the units have changed (1.333 micro seconds).
Have generalized the implementation of gen6_set_rps_thresholds function,
by removing the hard coding done in it as per 1.28 micro seconds.

v2: Renamed the local variables & removed superfluous comments (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++----------------------
 1 file changed, 32 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 339a034..e094e5d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3677,6 +3677,8 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
 {
 	int new_power;
+	u32 threshold_up = 0, threshold_down = 0; /* in % */
+	u32 ei_up = 0, ei_down = 0;
 
 	new_power = dev_priv->rps.power;
 	switch (dev_priv->rps.power) {
@@ -3709,59 +3711,53 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
 	switch (new_power) {
 	case LOW_POWER:
 		/* Upclock if more than 95% busy over 16ms */
-		I915_WRITE(GEN6_RP_UP_EI, 12500);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
+		ei_up = 16000;
+		threshold_up = 95;
 
 		/* Downclock if less than 85% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 85;
 		break;
 
 	case BETWEEN:
 		/* Upclock if more than 90% busy over 13ms */
-		I915_WRITE(GEN6_RP_UP_EI, 10250);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
+		ei_up = 13000;
+		threshold_up = 90;
 
 		/* Downclock if less than 75% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 75;
 		break;
 
 	case HIGH_POWER:
 		/* Upclock if more than 85% busy over 10ms */
-		I915_WRITE(GEN6_RP_UP_EI, 8000);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
+		ei_up = 10000;
+		threshold_up = 85;
 
 		/* Downclock if less than 60% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 60;
 		break;
 	}
 
+	I915_WRITE(GEN6_RP_UP_EI,
+		GT_INTERVAL_FROM_US(ei_up));
+	I915_WRITE(GEN6_RP_UP_THRESHOLD,
+		GT_INTERVAL_FROM_US((ei_up * threshold_up / 100)));
+
+	I915_WRITE(GEN6_RP_DOWN_EI,
+		GT_INTERVAL_FROM_US(ei_down));
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
+		GT_INTERVAL_FROM_US((ei_down * threshold_down / 100)));
+
+	 I915_WRITE(GEN6_RP_CONTROL,
+		    GEN6_RP_MEDIA_TURBO |
+		    GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		    GEN6_RP_MEDIA_IS_GFX |
+		    GEN6_RP_ENABLE |
+		    GEN6_RP_UP_BUSY_AVG |
+		    GEN6_RP_DOWN_IDLE_AVG);
+
 	dev_priv->rps.power = new_power;
 	dev_priv->rps.last_adj = 0;
 }
-- 
1.9.2

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[PATCH 6/8] drm/i915/skl: Updated the gen6_rps_limits function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

RP Interrupt Up/Down Frequency Limits register (A014) definition
has changed for SKL. Updated the gen6_rps_limits function as per that

v2: Renamed the function to intel_rps_limits (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e094e5d..c3a8704 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3657,7 +3657,7 @@ static void ironlake_disable_drps(struct drm_device *dev)
  * ourselves, instead of doing a rmw cycle (which might result in us clearing
  * all limits and the gpu stuck at whatever frequency it is at atm).
  */
-static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
+static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 {
 	u32 limits;
 
@@ -3667,9 +3667,15 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 	 * the hw runs at the minimal clock before selecting the desired
 	 * frequency, if the down threshold expires in that window we will not
 	 * receive a down interrupt. */
-	limits = dev_priv->rps.max_freq_softlimit << 24;
-	if (val <= dev_priv->rps.min_freq_softlimit)
-		limits |= dev_priv->rps.min_freq_softlimit << 16;
+	if (IS_GEN9(dev_priv->dev)) {
+		limits = (dev_priv->rps.max_freq_softlimit) << 23;
+		if (val <= dev_priv->rps.min_freq_softlimit)
+			limits |= (dev_priv->rps.min_freq_softlimit) << 14;
+	} else {
+		limits = dev_priv->rps.max_freq_softlimit << 24;
+		if (val <= dev_priv->rps.min_freq_softlimit)
+			limits |= dev_priv->rps.min_freq_softlimit << 16;
+	}
 
 	return limits;
 }
@@ -3810,7 +3816,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 	/* Make sure we continue to get interrupts
 	 * until we hit the minimum or maximum frequencies.
 	 */
-	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
 	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 
 	POSTING_READ(GEN6_RPNSWREQ);
-- 
1.9.2

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Re: [PATCH 5/8] drm/i915/skl: Restructured the gen6_set_rps_thresholds function

[Chris Wilson]

On Thu, Feb 26, 2015 at 06:19:41PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Prior to SKL, the time period programmed in Up/Down EI & Up/Down
> threshold registers was in units of 1.28 micro seconds. But for
> SKL, the units have changed (1.333 micro seconds).
> Have generalized the implementation of gen6_set_rps_thresholds function,
> by removing the hard coding done in it as per 1.28 micro seconds.
> 
> v2: Renamed the local variables & removed superfluous comments (Chris)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[PATCH 7/8] drm/i915/skl: Updated the gen9_enable_rps function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
us for older platforms. So updated the gen9_enable_rps function as per that.

v2: Updated to use new macro GT_INTERVAL_FROM_US

v3: Removed the initial setup of certain registers, from gen9_enable_rps,
    which gets overridden later from gen6_set_rps (Damien)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c3a8704..ce7ddbf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4084,21 +4084,20 @@ static void gen9_enable_rps(struct drm_device *dev)
 
 	gen6_init_rps_frequencies(dev);
 
-	I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
-	I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
-
-	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
-	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
-	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
-	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
-	I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
-	I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
+	/* Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RC_VIDEO_FREQ,
+		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
+
+	/* 1 second timeout*/
+	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, GT_INTERVAL_FROM_US(1000000));
+
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
-	I915_WRITE(GEN6_PMINTRMSK, 0x6);
-	I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
-		   GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
-		   GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
-		   GEN6_RP_DOWN_IDLE_AVG);
+
+	/* Leaning on the below call to gen6_set_rps to program/setup the
+	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
+	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
+	dev_priv->rps.power = HIGH_POWER; /* force a reset */
+	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
 
 	gen6_enable_rps_interrupts(dev);
 
-- 
1.9.2

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[PATCH 8/8] drm/i915/skl: Updated the i915_frequency_info debugfs function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Added support for SKL in the i915_frequency_info debugfs function

v2:
- corrected the handling of reqf (Damien)
- Reorderd the platform check for cagf (Ville)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e1e5d3..7bd79d7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1089,7 +1089,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Current P-state: %d\n",
 			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
-		   IS_BROADWELL(dev)) {
+		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
 		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1108,11 +1108,15 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 		reqf = I915_READ(GEN6_RPNSWREQ);
-		reqf &= ~GEN6_TURBO_DISABLE;
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-			reqf >>= 24;
-		else
-			reqf >>= 25;
+		if (IS_GEN9(dev))
+			reqf >>= 23;
+		else {
+			reqf &= ~GEN6_TURBO_DISABLE;
+			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+				reqf >>= 24;
+			else
+				reqf >>= 25;
+		}
 		reqf = intel_gpu_freq(dev_priv, reqf);
 
 		rpmodectl = I915_READ(GEN6_RP_CONTROL);
@@ -1126,7 +1130,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		if (IS_GEN9(dev))
+			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
 		else
 			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
@@ -1152,7 +1158,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 		seq_printf(m, "Render p-state ratio: %d\n",
-			   (gt_perf_status & 0xff00) >> 8);
+			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
 		seq_printf(m, "Render p-state VID: %d\n",
 			   gt_perf_status & 0xff);
 		seq_printf(m, "Render p-state limit: %d\n",
@@ -1177,14 +1183,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   GEN6_CURBSYTAVG_MASK);
 
 		max_freq = (rp_state_cap & 0xff0000) >> 16;
+		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
 		max_freq = (rp_state_cap & 0xff00) >> 8;
+		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
 		max_freq = rp_state_cap & 0xff;
+		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
-- 
1.9.2

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[PATCH 09/10] drm/i915/skl: Updated the act_freq_mhz_show sysfs function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Added support for SKL in the act_freq_mhz_show sysfs function

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 186ab95..57e1186 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -300,7 +300,9 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
 	} else {
 		u32 rpstat = I915_READ(GEN6_RPSTAT1);
-		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		if (IS_GEN9(dev_priv))
+			ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 			ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
 		else
 			ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
-- 
1.9.2

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[PATCH 10/10] drm/i915/skl: Enabling processing of Turbo interrupts

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Earlier Turbo interrupts were not being processed for SKL,
as something was amiss in turbo programming for SKL.
Now missing changes have been added, so enabling the Turbo
interrupt processing for SKL.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 07e257c..73089ff 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1696,11 +1696,6 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
  * the work queue. */
 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 {
-	/* TODO: RPS on GEN9+ is not supported yet. */
-	if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
-		      "GEN9+: unexpected RPS IRQ\n"))
-		return;
-
 	if (pm_iir & dev_priv->pm_rps_events) {
 		spin_lock(&dev_priv->irq_lock);
 		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
-- 
1.9.2

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Re: [PATCH 1/8] drm/i915/skl: Added new macros

[Chris Wilson]

On Thu, Feb 26, 2015 at 06:19:37PM +0530, akash.goel@intel.com wrote:
> +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
> +				INTERVAL_1_33_US(us) : \
> +				INTERVAL_1_28_US(us))

Just use IS_GEN9(dev_priv)
-Chris

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Re: [PATCH 1/8] drm/i915/skl: Added new macros

[Chris Wilson]

On Thu, Feb 26, 2015 at 12:50:16PM +0000, Chris Wilson wrote:
> On Thu, Feb 26, 2015 at 06:19:37PM +0530, akash.goel@intel.com wrote:
> > +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
> > +				INTERVAL_1_33_US(us) : \
> > +				INTERVAL_1_28_US(us))
> 
> Just use IS_GEN9(dev_priv)

Oh, and implicit paraemters to a macro are evil.
-Chris

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Re: [PATCH 8/8] drm/i915/skl: Updated the i915_frequency_info debugfs function

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5837
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  282/282              282/282
ILK                                  308/308              308/308
SNB                                  326/326              326/326
IVB                 -1              379/379              378/379
BYT                                  294/294              294/294
HSW                                  387/387              387/387
BDW                 -1              316/316              315/316
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*IVB  igt_gem_userptr_blits_minor-unsync-normal      PASS(2)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(12)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 1/8] drm/i915/skl: Added new macros

[Akash Goel]

On Thu, 2015-02-26 at 12:50 +0000, Chris Wilson wrote:
> On Thu, Feb 26, 2015 at 06:19:37PM +0530, akash.goel@intel.com wrote:
> > +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
> > +				INTERVAL_1_33_US(us) : \
> > +				INTERVAL_1_28_US(us))
> 
> Just use IS_GEN9(dev_priv)
Fine, will use 'dev_priv', actually missed the definition of '__I915__'
macro.
Is implicit use of 'dev_priv' fine ?. Actually saw several such
instances in i915_reg.h file, that's why used like this.

Best regards
Akash
> -Chris
> 


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Re: [PATCH 1/8] drm/i915/skl: Added new macros

[Chris Wilson]

On Thu, Mar 05, 2015 at 02:12:07PM +0530, Akash Goel wrote:
> On Thu, 2015-02-26 at 12:50 +0000, Chris Wilson wrote:
> > On Thu, Feb 26, 2015 at 06:19:37PM +0530, akash.goel@intel.com wrote:
> > > +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
> > > +				INTERVAL_1_33_US(us) : \
> > > +				INTERVAL_1_28_US(us))
> > 
> > Just use IS_GEN9(dev_priv)
> Fine, will use 'dev_priv', actually missed the definition of '__I915__'
> macro.
> Is implicit use of 'dev_priv' fine ?. Actually saw several such
> instances in i915_reg.h file, that's why used like this.

I am trying to wean i915 away from using the implicit arg as it is
making our code larger by the extra pointer dancing it forces upon us.
-Chris

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Re: [PATCH 3/8] drm/i915/skl: Updated the gen6_init_rps_frequencies function

[Ville Syrjälä]

On Thu, Feb 26, 2015 at 06:19:39PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL the frequency is specified in units of 16.66 MHZ, barring the
> RP_STATE_CAP(0x5998) register, which still reports frequency in units
> of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
> function for SKL, to store the frequency values as per the actual hardware unit.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1b36d0e..9dcfca6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4032,6 +4032,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
>  	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
>  	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
>  	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
> +	if (IS_SKYLAKE(dev)) {
> +		/* Store the frequency values in 16.66 MHZ units, which is
> +		   the natural hardware unit for SKL */
> +		dev_priv->rps.rp0_freq /= GEN9_FREQ_SCALER;
> +		dev_priv->rps.rp1_freq /= GEN9_FREQ_SCALER;
> +		dev_priv->rps.min_freq /= GEN9_FREQ_SCALER;
> +	}

Shouldn't these be multiplied instead of divided?

>  	/* hw_max = RP0 until we check for overclocking */
>  	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
>  
> -- 
> 1.9.2
> 
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Re: [PATCH 2/8] drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()

[Ville Syrjälä]

On Thu, Feb 26, 2015 at 06:19:38PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL, frequency is specified in units of 16.66 MHZ.
> Updated the intel_gpu_freq() and intel_freq_opecode() functions
> to do the conversion appropriately.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7dcb5b6..1b36d0e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6660,7 +6660,9 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
>  {
> -	if (IS_CHERRYVIEW(dev_priv->dev))
> +	if (IS_GEN9(dev_priv->dev))
> +		return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
> +	else if (IS_CHERRYVIEW(dev_priv->dev))
>  		return chv_gpu_freq(dev_priv, val);
>  	else if (IS_VALLEYVIEW(dev_priv->dev))
>  		return byt_gpu_freq(dev_priv, val);
> @@ -6670,7 +6672,9 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
>  
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  {
> -	if (IS_CHERRYVIEW(dev_priv->dev))
> +	if (IS_GEN9(dev_priv->dev))
> +		return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
> +	else if (IS_CHERRYVIEW(dev_priv->dev))
>  		return chv_freq_opcode(dev_priv, val);
>  	else if (IS_VALLEYVIEW(dev_priv->dev))
>  		return byt_freq_opcode(dev_priv, val);
> -- 
> 1.9.2
> 
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Re: [PATCH 4/8] drm/i915/skl: Updated the gen6_set_rps function

[Ville Syrjälä]

On Thu, Feb 26, 2015 at 06:19:40PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL, the frequency is programmed differently in RPNSWREQ (A008)
> register (from bits 23 to 31, compared to bits 24 to 31). So updated
> the gen6_set_rps function, as per this change.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

A bit hard to see since the GEN9_FREQUENCY() define was added in another
patch, but checking that against the spec tells me the shift is correct.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9dcfca6..339a034 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3798,7 +3798,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
>  	if (val != dev_priv->rps.cur_freq) {
>  		gen6_set_rps_thresholds(dev_priv, val);
>  
> -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +		if (IS_GEN9(dev))
> +			I915_WRITE(GEN6_RPNSWREQ,
> +				   GEN9_FREQUENCY(val));
> +		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			I915_WRITE(GEN6_RPNSWREQ,
>  				   HSW_FREQUENCY(val));
>  		else
> -- 
> 1.9.2
> 
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Re: [PATCH 6/8] drm/i915/skl: Updated the gen6_rps_limits function

[Ville Syrjälä]

On Thu, Feb 26, 2015 at 06:19:42PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> RP Interrupt Up/Down Frequency Limits register (A014) definition
> has changed for SKL. Updated the gen6_rps_limits function as per that
> 
> v2: Renamed the function to intel_rps_limits (Chris)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e094e5d..c3a8704 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3657,7 +3657,7 @@ static void ironlake_disable_drps(struct drm_device *dev)
>   * ourselves, instead of doing a rmw cycle (which might result in us clearing
>   * all limits and the gpu stuck at whatever frequency it is at atm).
>   */
> -static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
> +static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
>  {
>  	u32 limits;
>  
> @@ -3667,9 +3667,15 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
>  	 * the hw runs at the minimal clock before selecting the desired
>  	 * frequency, if the down threshold expires in that window we will not
>  	 * receive a down interrupt. */
> -	limits = dev_priv->rps.max_freq_softlimit << 24;
> -	if (val <= dev_priv->rps.min_freq_softlimit)
> -		limits |= dev_priv->rps.min_freq_softlimit << 16;
> +	if (IS_GEN9(dev_priv->dev)) {
> +		limits = (dev_priv->rps.max_freq_softlimit) << 23;
> +		if (val <= dev_priv->rps.min_freq_softlimit)
> +			limits |= (dev_priv->rps.min_freq_softlimit) << 14;
> +	} else {
> +		limits = dev_priv->rps.max_freq_softlimit << 24;
> +		if (val <= dev_priv->rps.min_freq_softlimit)
> +			limits |= dev_priv->rps.min_freq_softlimit << 16;
> +	}
>  
>  	return limits;
>  }
> @@ -3810,7 +3816,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
>  	/* Make sure we continue to get interrupts
>  	 * until we hit the minimum or maximum frequencies.
>  	 */
> -	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
> +	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
>  	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
>  
>  	POSTING_READ(GEN6_RPNSWREQ);
> -- 
> 1.9.2
> 
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Re: [PATCH 09/10] drm/i915/skl: Updated the act_freq_mhz_show sysfs function

[Ville Syrjälä]

On Thu, Feb 26, 2015 at 06:19:45PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Added support for SKL in the act_freq_mhz_show sysfs function
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Again required a bit of mail juggling to double chekc the definition,
but looks correct.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_sysfs.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 186ab95..57e1186 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -300,7 +300,9 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
>  		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
>  	} else {
>  		u32 rpstat = I915_READ(GEN6_RPSTAT1);
> -		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +		if (IS_GEN9(dev_priv))
> +			ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> +		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  			ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
>  		else
>  			ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> -- 
> 1.9.2
> 
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> Intel-gfx@lists.freedesktop.org
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-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 3/8] drm/i915/skl: Updated the gen6_init_rps_frequencies function

[Akash Goel]

On Thu, 2015-03-05 at 12:14 +0200, Ville Syrjälä wrote:
> On Thu, Feb 26, 2015 at 06:19:39PM +0530, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > On SKL the frequency is specified in units of 16.66 MHZ, barring the
> > RP_STATE_CAP(0x5998) register, which still reports frequency in units
> > of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
> > function for SKL, to store the frequency values as per the actual hardware unit.
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 1b36d0e..9dcfca6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4032,6 +4032,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
> >  	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
> >  	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
> >  	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
> > +	if (IS_SKYLAKE(dev)) {
> > +		/* Store the frequency values in 16.66 MHZ units, which is
> > +		   the natural hardware unit for SKL */
> > +		dev_priv->rps.rp0_freq /= GEN9_FREQ_SCALER;
> > +		dev_priv->rps.rp1_freq /= GEN9_FREQ_SCALER;
> > +		dev_priv->rps.min_freq /= GEN9_FREQ_SCALER;
> > +	}
> 
> Shouldn't these be multiplied instead of divided?
So sorry for this blooper, thanks for spotting it.
Did it correctly in debugfs but faltered here. 
> 
> >  	/* hw_max = RP0 until we check for overclocking */
> >  	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
> >  
> > -- 
> > 1.9.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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