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From: Daniel Vetter <daniel@ffwll.ch>
To: "Song, Ruiling" <ruiling.song@intel.com>
Cc: "Vetter, Daniel" <daniel.vetter@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Yang, Rong R" <rong.r.yang@intel.com>,
	"beignet@lists.freedesktop.org" <beignet@lists.freedesktop.org>,
	"Weinehall, David" <david.weinehall@intel.com>
Subject: Re: [Intel-gfx] Preventing zero GPU virtual address allocation
Date: Thu, 5 Mar 2015 13:52:51 +0100	[thread overview]
Message-ID: <20150305125251.GA18775@phenom.ffwll.local> (raw)
In-Reply-To: <148B1B7A67D1C24B9EF0BE42EA4977062B7DCBFB@SHSMSX101.ccr.corp.intel.com>

On Thu, Mar 05, 2015 at 02:56:52AM +0000, Song, Ruiling wrote:
> Hi Daniel,
> 
> OpenCL language support NULL pointer, using zero as the NULL pointer is
> the obvious way. That is zero will be treated as invalid address.  Then
> it requires drm won't allocate zero to drm buffer. And David in CC
> list has help us make a patch, please see attached. The logic is only
> for ppgtt, and he said zero offset is used under ggtt. My question is
> what is offset zero used under ggtt? Will it make sure zero is not
> allocatable to drm buffer object?

The code in i915_gem_execbuf.c already supports an optional bias to avoid
putting a buffer into the first few kb. See __EXEC_OBJECT_NEEDS_BIAS. I
suggest you expose this to userspace, which also address your issue that
you didn't add an abi revision flag.

And since this is abi I need open-source userspace and all that.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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  reply	other threads:[~2015-03-05 12:52 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-05  2:56 Preventing zero GPU virtual address allocation Song, Ruiling
2015-03-05 12:52 ` Daniel Vetter [this message]
2015-03-05 13:01   ` Chris Wilson
2015-03-05 15:27     ` [Intel-gfx] " Daniel Vetter
2015-03-05 21:07       ` Chris Wilson
2015-03-09 15:46         ` Jesse Barnes
2015-03-09 15:49           ` Jesse Barnes
2015-03-06  2:11       ` [Intel-gfx] " Zou, Nanhai
2015-03-06  8:39         ` [Beignet] " Chris Wilson
2015-03-09  2:34           ` Zou, Nanhai
2015-03-09 12:02             ` [Intel-gfx] " Chris Wilson
2015-03-10  1:57               ` Zou, Nanhai
2015-03-13  9:10               ` [Beignet] " David Weinehall
2015-03-13  9:18                 ` [Intel-gfx] " Chris Wilson
2015-03-13  9:27                 ` Daniel Vetter
2015-03-13 16:58                   ` [Beignet] " Chris Wilson
2015-03-13 17:13                     ` [Intel-gfx] " Daniel Vetter
2015-03-13 17:34                       ` [Beignet] " Chris Wilson
2015-03-13 17:49                         ` [Intel-gfx] " Daniel Vetter
2015-03-16  2:29                       ` [Beignet] " Song, Ruiling
2015-03-16  8:52                         ` Daniel Vetter
2015-03-16 20:10                           ` Jesse Barnes
2015-03-17  1:19                             ` [Intel-gfx] " Zhigang Gong
2015-03-17  2:29                             ` Zou, Nanhai
2015-03-17 15:13                               ` [Beignet] " Jesse Barnes
2015-03-19  3:22                                 ` [Intel-gfx] " Song, Ruiling
2015-03-19 10:09                                   ` [Beignet] " David Weinehall
2015-03-19 14:58                                     ` Daniel Vetter
2015-03-20  3:01                                       ` Song, Ruiling
2015-03-17 10:01                             ` Daniel Vetter
2015-03-16 20:11                           ` Jesse Barnes

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