Re: [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Mar 05, 2015 at 07:33:08PM +0530, Vijay Purushothaman wrote:
> This patch implements latest PHY changes in Gain, prop and int co-efficients
> based on the vco freq.
> 
> v2: Split the original changes into multiple smaller patches based on
> review by Ville
> 
> v3: Addressed Ville's review comments. Fixed the error introduced in v2.
> Clear the old bits before we modify those bits as part of RMW.
> 
> v4: TDC target cnt is 10 bits and not 8 bits (Ville)
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    2 ++
>  drivers/gpu/drm/i915/intel_display.c |   43 ++++++++++++++++++++++++----------
>  2 files changed, 33 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1a0f94e..14b560b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
>  
>  #define _CHV_PLL_DW8_CH0		0x8020
>  #define _CHV_PLL_DW8_CH1		0x81A0
> +#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> +#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
>  #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>  
>  #define _CHV_PLL_DW9_CH0		0x8024
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6c5a5a9..3eb0946 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	int pipe = crtc->pipe;
>  	int dpll_reg = DPLL(crtc->pipe);
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> -	u32 loopfilter, intcoeff;
> +	u32 loopfilter, tribuf_calcntr;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>  	u32 dpio_val;
> -	int refclk;
> +	int vco;
>  
>  	bestn = pipe_config->dpll.n;
>  	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
> @@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	bestm2 = pipe_config->dpll.m2 >> 22;
>  	bestp1 = pipe_config->dpll.p1;
>  	bestp2 = pipe_config->dpll.p2;
> +	vco = pipe_config->dpll.vco;
>  	dpio_val = 0;
> +	loopfilter = 0;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6187,18 +6189,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
>  
>  	/* Loop filter */
> -	refclk = i9xx_get_refclk(crtc, 0);
> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> -	if (refclk == 100000)
> -		intcoeff = 11;
> -	else if (refclk == 38400)
> -		intcoeff = 10;
> -	else
> -		intcoeff = 9;
> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> +	if (vco == 5400000) {
> +		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x9;
> +	} else if (vco <= 6200000) {
> +		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x9;
> +	} else if (vco <= 6480000) {
> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x8;
> +	} else {
> +		/* Not supported. Apply the same limits as in the max case */
> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0;
> +	}
>  	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>  
> +	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
> +	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
> +	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
> +
>  	/* AFC Recal */
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>  			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> -- 
> 1.7.9.5
> 
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-- 
Ville Syrjälä
Intel OTC
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