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From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 0/6] SKL post-enable power well hook (v2)
Date: Mon, 9 Mar 2015 10:00:11 +0100	[thread overview]
Message-ID: <20150309090011.GI24485@phenom.ffwll.local> (raw)
In-Reply-To: <CA+gsUGQ_Py+6T+XXaYD1qRT7uayvzsb8-7E9rn4WFQ5W0HP6qA@mail.gmail.com>

On Fri, Mar 06, 2015 at 04:28:16PM -0300, Paulo Zanoni wrote:
> 2015-03-06 15:50 GMT-03:00 Damien Lespiau <damien.lespiau@intel.com>:
> > Here's a new spin of the series, restoring interrupt registers and DDI
> > translation tables when re-enabling power-wells.
> >
> > v2:
> >   - Don't run the post-enable hook when the power well is already enabled
> >   - Put the DDI patch with the rest of the serise
> 
> For everything: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

All applied, thanks.
-Daniel

> 
> >
> > --
> > Damien
> >
> >
> > Damien Lespiau (6):
> >   drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
> >   drm/i915/skl: Introduce enable_requested and is_enabled in the power
> >     well code
> >   drm/i915/skl: Mirror what we do on HSW for the power well enable log
> >     message
> >   drm/i915/skl: Restore pipe interrupt registers after power well
> >     enabling
> >   drm/i915: Remove unused condition in hsw_power_well_post_enable()
> >   drm/i915/skl: Restore the DDI translation tables when enabling PW1
> >
> >  drivers/gpu/drm/i915/i915_irq.c         | 19 +++++++++----
> >  drivers/gpu/drm/i915/intel_drv.h        |  3 +-
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 50 ++++++++++++++++++++++++++++-----
> >  3 files changed, 59 insertions(+), 13 deletions(-)
> >
> > --
> > 1.8.3.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

      reply	other threads:[~2015-03-09  8:58 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-06 18:50 [PATCH 0/6] SKL post-enable power well hook (v2) Damien Lespiau
2015-03-06 18:50 ` [PATCH 1/6] drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask Damien Lespiau
2015-03-09  8:50   ` Daniel Vetter
2015-03-06 18:50 ` [PATCH 2/6] drm/i915/skl: Introduce enable_requested and is_enabled in the power well code Damien Lespiau
2015-03-06 18:50 ` [PATCH 3/6] drm/i915/skl: Mirror what we do on HSW for the power well enable log message Damien Lespiau
2015-03-06 18:50 ` [PATCH 4/6] drm/i915/skl: Restore pipe interrupt registers after power well enabling Damien Lespiau
2015-03-06 18:50 ` [PATCH 5/6] drm/i915: Remove unused condition in hsw_power_well_post_enable() Damien Lespiau
2015-03-06 18:50 ` [PATCH 6/6] drm/i915/skl: Restore the DDI translation tables when enabling PW1 Damien Lespiau
2015-03-07  1:32   ` shuang.he
2015-03-06 19:28 ` [PATCH 0/6] SKL post-enable power well hook (v2) Paulo Zanoni
2015-03-09  9:00   ` Daniel Vetter [this message]

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