From: Daniel Vetter <daniel@ffwll.ch>
To: "Purushothaman, Vijay A" <vijay.a.purushothaman@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v4 10/12] drm/i915: Program PFI credits for VLV
Date: Tue, 10 Mar 2015 11:28:33 +0100 [thread overview]
Message-ID: <20150310102833.GL3800@phenom.ffwll.local> (raw)
In-Reply-To: <54FEC1DF.5080204@linux.intel.com>
On Tue, Mar 10, 2015 at 03:35:19PM +0530, Purushothaman, Vijay A wrote:
> On 3/6/2015 12:49 AM, ville.syrjala@linux.intel.com wrote:
> >From: Vidya Srinivas <vidya.srinivas@intel.com>
> >
> >PFI credit programming is required when CD clock (related to data flow from
> >display pipeline to end display) is greater than CZ clock (related to data
> >flow from memory to display plane). This programming should be done when all
> >planes are OFF to avoid intermittent hangs while accessing memory even from
> >different Gfx units (not just display).
> >
> >If cdclk/czclk >=1, PFI credits could be set as any number. To get better
> >performance, larger PFI credit can be assigned to PND. Otherwise if
> >cdclk/czclk<1, the default PFI credit of 8 should be set.
> >
> >v2:
> > - Change log to lower log level instead of DRM_ERROR
> > - Change function name to valleyview_program_pfi_credits
> > - Move program PFI credits to modeset_init instead of intel_set_mode
> > - Change magic numbers to logical constants
> >
> >[vsyrjala v3:
> > - only program in response to cdclk update
> > - program the credits also when cdclk<czclk
> > - add CHV bits
> > v4:
> > - Change CHV cdclk<czclk credits to 12 (Vijay)]
> >
> >Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> >Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> >Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Pulled in the remaining 4 patches from this series, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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next prev parent reply other threads:[~2015-03-10 10:26 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-05 19:19 [PATCH v2 00/12] drm/i915: Redo VLV/CHV watermark code (v2) ville.syrjala
2015-03-05 19:19 ` [PATCH v2 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8 ville.syrjala
2015-03-09 3:39 ` Arun R Murthy
2015-03-05 19:19 ` [PATCH v2 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines ville.syrjala
2015-03-09 3:48 ` Arun R Murthy
2015-03-09 14:53 ` Ville Syrjälä
2015-03-05 19:19 ` [PATCH 03/12] drm/i915: Simplify VLV drain latency computation ville.syrjala
2015-03-05 19:19 ` [PATCH 04/12] drm/i915: Hide VLV DDL precision handling ville.syrjala
2015-03-09 4:02 ` Arun R Murthy
2015-03-05 19:19 ` [PATCH 05/12] drm/i915: Reorganize VLV DDL setup ville.syrjala
2015-03-05 19:19 ` [PATCH v2 06/12] drm/i915: Pass plane to vlv_compute_drain_latency() ville.syrjala
2015-03-05 19:19 ` [PATCH v2 07/12] drm/i915: Read out display FIFO size on VLV/CHV ville.syrjala
2015-03-05 19:19 ` [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled " ville.syrjala
2015-03-06 17:29 ` Daniel Vetter
2015-03-05 19:19 ` [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code ville.syrjala
2015-03-06 17:31 ` Jesse Barnes
2015-03-06 17:40 ` Daniel Vetter
2015-03-06 18:14 ` Ville Syrjälä
2015-03-06 20:28 ` Jesse Barnes
2015-03-10 10:26 ` Daniel Vetter
2015-03-10 11:27 ` Ville Syrjälä
2015-03-05 19:19 ` [PATCH v4 10/12] drm/i915: Program PFI credits for VLV ville.syrjala
2015-03-10 10:05 ` Purushothaman, Vijay A
2015-03-10 10:28 ` Daniel Vetter [this message]
2015-03-05 19:19 ` [PATCH v3 11/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV ville.syrjala
2015-03-09 4:23 ` Arun R Murthy
2015-03-05 19:19 ` [PATCH 12/12] drm/i915: Disable DDR DVFS " ville.syrjala
2015-03-06 17:31 ` Jesse Barnes
2015-03-09 4:44 ` Arun R Murthy
2015-03-09 15:00 ` Ville Syrjälä
2015-03-09 15:34 ` Daniel Vetter
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