[PATCH v4 00/11] Added missing changes for Turbo feature on SKL

[PATCH v4 00/11] Added missing changes for Turbo feature on SKL

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

This patch series add the missing changes, required for proper
functioning of the Turbo feature on SKL. Most of the changes are
mainly due to the fact that on SKL, the frequency has to be programmed
in units of 16.66 MHZ and the time period value programmed in Up/Down
EI & threshold registers, is in units of 1.333 micro seconds.
In this version, review comments from Chris & Ville have been addressed
and a new patch has been added to enable the RPS interrupts programming
for SKL also.

Akash Goel (11):
  drm/i915/skl: Added new macros
  drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()
  drm/i915/skl: Updated the gen6_init_rps_frequencies function
  drm/i915/skl: Updated the gen6_set_rps function
  drm/i915/skl: Restructured the gen6_set_rps_thresholds function
  drm/i915/skl: Updated the gen6_rps_limits function
  drm/i915/skl: Updated the gen9_enable_rps function
  drm/i915/skl: Updated the i915_frequency_info debugfs function
  drm/i915/skl: Updated the act_freq_mhz_show sysfs function
  drm/i915/skl: Enabling processing of Turbo interrupts
  drm/i915/skl: Enable the RPS interrupts programming

 drivers/gpu/drm/i915/i915_debugfs.c |  25 ++++--
 drivers/gpu/drm/i915/i915_drv.h     |   1 +
 drivers/gpu/drm/i915/i915_irq.c     |   5 --
 drivers/gpu/drm/i915/i915_reg.h     |   9 +++
 drivers/gpu/drm/i915/i915_sysfs.c   |   4 +-
 drivers/gpu/drm/i915/intel_pm.c     | 147 ++++++++++++++++++------------------
 6 files changed, 105 insertions(+), 86 deletions(-)

-- 
1.9.2

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[PATCH 01/11] drm/i915/skl: Added new macros

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
have changed slightly. Also on SKL, frequency is specified in
units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
platforms and the time values are expressed in units of 1.33 us,
compared to 1.28 us for earlier platforms.
Added new macros for the aforementioned changes.

v2: Renamed the GT_FREQ_FROM_PERIOD macro to GT_INTERVAL_FROM_US (Damien)

v3: Removed the implicit use of dev_priv in GT_INTERVAL_FROM_US macro (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b384b72..f676dc8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2414,6 +2414,7 @@ struct drm_i915_cmd_table {
 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
 
 #define GT_FREQUENCY_MULTIPLIER 50
+#define GEN9_FREQ_SCALER 3
 
 #include "i915_trace.h"
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 56b97c4..05ab344 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2427,6 +2427,12 @@ enum skl_disp_power_wells {
 #define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
 #define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
 
+#define INTERVAL_1_28_US(us)	(((us) * 100) >> 7)
+#define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
+#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
+				INTERVAL_1_33_US(us) : \
+				INTERVAL_1_28_US(us))
+
 /*
  * Logical Context regs
  */
@@ -6080,6 +6086,7 @@ enum skl_disp_power_wells {
 #define   GEN6_TURBO_DISABLE			(1<<31)
 #define   GEN6_FREQUENCY(x)			((x)<<25)
 #define   HSW_FREQUENCY(x)			((x)<<24)
+#define   GEN9_FREQUENCY(x)			((x)<<23)
 #define   GEN6_OFFSET(x)			((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
 #define GEN6_RC_VIDEO_FREQ			0xA00C
@@ -6098,8 +6105,10 @@ enum skl_disp_power_wells {
 #define GEN6_RPSTAT1				0xA01C
 #define   GEN6_CAGF_SHIFT			8
 #define   HSW_CAGF_SHIFT			7
+#define   GEN9_CAGF_SHIFT			23
 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
+#define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
 #define GEN6_RP_CONTROL				0xA024
 #define   GEN6_RP_MEDIA_TURBO			(1<<11)
 #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
-- 
1.9.2

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Re: [PATCH 01/11] drm/i915/skl: Added new macros

[Ville Syrjälä]

On Fri, Mar 06, 2015 at 11:07:14AM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
> have changed slightly. Also on SKL, frequency is specified in
> units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
> platforms and the time values are expressed in units of 1.33 us,
> compared to 1.28 us for earlier platforms.
> Added new macros for the aforementioned changes.
> 
> v2: Renamed the GT_FREQ_FROM_PERIOD macro to GT_INTERVAL_FROM_US (Damien)
> 
> v3: Removed the implicit use of dev_priv in GT_INTERVAL_FROM_US macro (Chris)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b384b72..f676dc8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2414,6 +2414,7 @@ struct drm_i915_cmd_table {
>  #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
>  
>  #define GT_FREQUENCY_MULTIPLIER 50
> +#define GEN9_FREQ_SCALER 3
>  
>  #include "i915_trace.h"
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 56b97c4..05ab344 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2427,6 +2427,12 @@ enum skl_disp_power_wells {
>  #define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
>  #define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
>  
> +#define INTERVAL_1_28_US(us)	(((us) * 100) >> 7)
> +#define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
> +#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> +				INTERVAL_1_33_US(us) : \
> +				INTERVAL_1_28_US(us))
> +
>  /*
>   * Logical Context regs
>   */
> @@ -6080,6 +6086,7 @@ enum skl_disp_power_wells {
>  #define   GEN6_TURBO_DISABLE			(1<<31)
>  #define   GEN6_FREQUENCY(x)			((x)<<25)
>  #define   HSW_FREQUENCY(x)			((x)<<24)
> +#define   GEN9_FREQUENCY(x)			((x)<<23)
>  #define   GEN6_OFFSET(x)			((x)<<19)
>  #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
>  #define GEN6_RC_VIDEO_FREQ			0xA00C
> @@ -6098,8 +6105,10 @@ enum skl_disp_power_wells {
>  #define GEN6_RPSTAT1				0xA01C
>  #define   GEN6_CAGF_SHIFT			8
>  #define   HSW_CAGF_SHIFT			7
> +#define   GEN9_CAGF_SHIFT			23
>  #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
>  #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
> +#define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
>  #define GEN6_RP_CONTROL				0xA024
>  #define   GEN6_RP_MEDIA_TURBO			(1<<11)
>  #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
> -- 
> 1.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 02/11] drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, frequency is specified in units of 16.66 MHZ.
Updated the intel_gpu_freq() and intel_freq_opecode() functions
to do the conversion appropriately.

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e710b43..1b44eee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6708,7 +6708,9 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
-	if (IS_CHERRYVIEW(dev_priv->dev))
+	if (IS_GEN9(dev_priv->dev))
+		return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
+	else if (IS_CHERRYVIEW(dev_priv->dev))
 		return chv_gpu_freq(dev_priv, val);
 	else if (IS_VALLEYVIEW(dev_priv->dev))
 		return byt_gpu_freq(dev_priv, val);
@@ -6718,7 +6720,9 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
-	if (IS_CHERRYVIEW(dev_priv->dev))
+	if (IS_GEN9(dev_priv->dev))
+		return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
+	else if (IS_CHERRYVIEW(dev_priv->dev))
 		return chv_freq_opcode(dev_priv, val);
 	else if (IS_VALLEYVIEW(dev_priv->dev))
 		return byt_freq_opcode(dev_priv, val);
-- 
1.9.2

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[PATCH 03/11] drm/i915/skl: Updated the gen6_init_rps_frequencies function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
function for SKL, to store the frequency values as per the actual hardware unit.

v2: Corrected the conversion from 50 to 16.66 MHZ (Ville)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1b44eee..81eaa0c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4080,6 +4080,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
 	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
 	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
 	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
+	if (IS_SKYLAKE(dev)) {
+		/* Store the frequency values in 16.66 MHZ units, which is
+		   the natural hardware unit for SKL */
+		dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
+	}
 	/* hw_max = RP0 until we check for overclocking */
 	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
 
-- 
1.9.2

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Re: [PATCH 03/11] drm/i915/skl: Updated the gen6_init_rps_frequencies function

[Ville Syrjälä]

On Fri, Mar 06, 2015 at 11:07:16AM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL the frequency is specified in units of 16.66 MHZ, barring the
> RP_STATE_CAP(0x5998) register, which still reports frequency in units
> of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
> function for SKL, to store the frequency values as per the actual hardware unit.
> 
> v2: Corrected the conversion from 50 to 16.66 MHZ (Ville)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1b44eee..81eaa0c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4080,6 +4080,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
>  	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
>  	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
>  	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
> +	if (IS_SKYLAKE(dev)) {
> +		/* Store the frequency values in 16.66 MHZ units, which is
> +		   the natural hardware unit for SKL */
> +		dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
> +		dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
> +		dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
> +	}
>  	/* hw_max = RP0 until we check for overclocking */
>  	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
>  
> -- 
> 1.9.2
> 
> _______________________________________________
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-- 
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[PATCH 04/11] drm/i915/skl: Updated the gen6_set_rps function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, the frequency is programmed differently in RPNSWREQ (A008)
register (from bits 23 to 31, compared to bits 24 to 31). So updated
the gen6_set_rps function, as per this change.

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 81eaa0c..1d7f6d1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3846,7 +3846,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		if (IS_GEN9(dev))
+			I915_WRITE(GEN6_RPNSWREQ,
+				   GEN9_FREQUENCY(val));
+		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   HSW_FREQUENCY(val));
 		else
-- 
1.9.2

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[PATCH 05/11] drm/i915/skl: Restructured the gen6_set_rps_thresholds function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Prior to SKL, the time period programmed in Up/Down EI & Up/Down
threshold registers was in units of 1.28 micro seconds. But for
SKL, the units have changed (1.333 micro seconds).
Have generalized the implementation of gen6_set_rps_thresholds function,
by removing the hard coding done in it as per 1.28 micro seconds.

v2: Renamed the local variables & removed superfluous comments (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++----------------------
 1 file changed, 32 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1d7f6d1..b9b6fc1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3725,6 +3725,8 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
 {
 	int new_power;
+	u32 threshold_up = 0, threshold_down = 0; /* in % */
+	u32 ei_up = 0, ei_down = 0;
 
 	new_power = dev_priv->rps.power;
 	switch (dev_priv->rps.power) {
@@ -3757,59 +3759,53 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
 	switch (new_power) {
 	case LOW_POWER:
 		/* Upclock if more than 95% busy over 16ms */
-		I915_WRITE(GEN6_RP_UP_EI, 12500);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
+		ei_up = 16000;
+		threshold_up = 95;
 
 		/* Downclock if less than 85% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 85;
 		break;
 
 	case BETWEEN:
 		/* Upclock if more than 90% busy over 13ms */
-		I915_WRITE(GEN6_RP_UP_EI, 10250);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
+		ei_up = 13000;
+		threshold_up = 90;
 
 		/* Downclock if less than 75% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 75;
 		break;
 
 	case HIGH_POWER:
 		/* Upclock if more than 85% busy over 10ms */
-		I915_WRITE(GEN6_RP_UP_EI, 8000);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
+		ei_up = 10000;
+		threshold_up = 85;
 
 		/* Downclock if less than 60% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 60;
 		break;
 	}
 
+	I915_WRITE(GEN6_RP_UP_EI,
+		GT_INTERVAL_FROM_US(dev_priv, ei_up));
+	I915_WRITE(GEN6_RP_UP_THRESHOLD,
+		GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
+
+	I915_WRITE(GEN6_RP_DOWN_EI,
+		GT_INTERVAL_FROM_US(dev_priv, ei_down));
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
+		GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
+
+	 I915_WRITE(GEN6_RP_CONTROL,
+		    GEN6_RP_MEDIA_TURBO |
+		    GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		    GEN6_RP_MEDIA_IS_GFX |
+		    GEN6_RP_ENABLE |
+		    GEN6_RP_UP_BUSY_AVG |
+		    GEN6_RP_DOWN_IDLE_AVG);
+
 	dev_priv->rps.power = new_power;
 	dev_priv->rps.last_adj = 0;
 }
-- 
1.9.2

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[PATCH 06/11] drm/i915/skl: Updated the gen6_rps_limits function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

RP Interrupt Up/Down Frequency Limits register (A014) definition
has changed for SKL. Updated the gen6_rps_limits function as per that

v2: Renamed the function to intel_rps_limits (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9b6fc1..c49950f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3705,7 +3705,7 @@ static void ironlake_disable_drps(struct drm_device *dev)
  * ourselves, instead of doing a rmw cycle (which might result in us clearing
  * all limits and the gpu stuck at whatever frequency it is at atm).
  */
-static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
+static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 {
 	u32 limits;
 
@@ -3715,9 +3715,15 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 	 * the hw runs at the minimal clock before selecting the desired
 	 * frequency, if the down threshold expires in that window we will not
 	 * receive a down interrupt. */
-	limits = dev_priv->rps.max_freq_softlimit << 24;
-	if (val <= dev_priv->rps.min_freq_softlimit)
-		limits |= dev_priv->rps.min_freq_softlimit << 16;
+	if (IS_GEN9(dev_priv->dev)) {
+		limits = (dev_priv->rps.max_freq_softlimit) << 23;
+		if (val <= dev_priv->rps.min_freq_softlimit)
+			limits |= (dev_priv->rps.min_freq_softlimit) << 14;
+	} else {
+		limits = dev_priv->rps.max_freq_softlimit << 24;
+		if (val <= dev_priv->rps.min_freq_softlimit)
+			limits |= dev_priv->rps.min_freq_softlimit << 16;
+	}
 
 	return limits;
 }
@@ -3858,7 +3864,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 	/* Make sure we continue to get interrupts
 	 * until we hit the minimum or maximum frequencies.
 	 */
-	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
 	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 
 	POSTING_READ(GEN6_RPNSWREQ);
-- 
1.9.2

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[PATCH 07/11] drm/i915/skl: Updated the gen9_enable_rps function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
us for older platforms. So updated the gen9_enable_rps function as per that.

v2: Updated to use new macro GT_INTERVAL_FROM_US

v3: Removed the initial setup of certain registers, from gen9_enable_rps,
    which gets overridden later from gen6_set_rps (Damien)

v4: Removed the enabling of rps interrupts, from gen9_enable_rps.
    To be done from intel_gen6_powersave_work only, as done for other
    platforms also.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c49950f..6273c282 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4132,23 +4132,21 @@ static void gen9_enable_rps(struct drm_device *dev)
 
 	gen6_init_rps_frequencies(dev);
 
-	I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
-	I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
-
-	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
-	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
-	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
-	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
-	I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
-	I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
+	/* Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RC_VIDEO_FREQ,
+		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
+
+	/* 1 second timeout*/
+	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
+		GT_INTERVAL_FROM_US(dev_priv, 1000000));
+
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
-	I915_WRITE(GEN6_PMINTRMSK, 0x6);
-	I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
-		   GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
-		   GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
-		   GEN6_RP_DOWN_IDLE_AVG);
 
-	gen6_enable_rps_interrupts(dev);
+	/* Leaning on the below call to gen6_set_rps to program/setup the
+	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
+	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
+	dev_priv->rps.power = HIGH_POWER; /* force a reset */
+	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
-- 
1.9.2

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Re: [PATCH 07/11] drm/i915/skl: Updated the gen9_enable_rps function

[Jesse Barnes]

On 03/05/2015 09:37 PM, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
> to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
> Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
> us for older platforms. So updated the gen9_enable_rps function as per that.
> 
> v2: Updated to use new macro GT_INTERVAL_FROM_US
> 
> v3: Removed the initial setup of certain registers, from gen9_enable_rps,
>     which gets overridden later from gen6_set_rps (Damien)
> 
> v4: Removed the enabling of rps interrupts, from gen9_enable_rps.
>     To be done from intel_gen6_powersave_work only, as done for other
>     platforms also.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++++++---------------
>  1 file changed, 13 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c49950f..6273c282 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4132,23 +4132,21 @@ static void gen9_enable_rps(struct drm_device *dev)
>  
>  	gen6_init_rps_frequencies(dev);
>  
> -	I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
> -	I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
> -
> -	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
> -	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
> -	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
> -	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
> -	I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
> -	I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
> +	/* Program defaults and thresholds for RPS*/
> +	I915_WRITE(GEN6_RC_VIDEO_FREQ,
> +		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
> +
> +	/* 1 second timeout*/
> +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
> +		GT_INTERVAL_FROM_US(dev_priv, 1000000));
> +
>  	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
> -	I915_WRITE(GEN6_PMINTRMSK, 0x6);
> -	I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
> -		   GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
> -		   GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
> -		   GEN6_RP_DOWN_IDLE_AVG);
>  
> -	gen6_enable_rps_interrupts(dev);
> +	/* Leaning on the below call to gen6_set_rps to program/setup the
> +	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
> +	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
> +	dev_priv->rps.power = HIGH_POWER; /* force a reset */

Are you also sure that dev_priv->rps.cur_freq != min_freq_softlimit at
this point?  That's the condition for calling into the threshold update
function (maybe gen6_set_rps should check both variables though).

> +	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>  }
> 

I'm assuming these match the latest SKL PM bits, but either way can be
updated later based on tuning.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 07/11] drm/i915/skl: Updated the gen9_enable_rps function

[Chris Wilson]

On Wed, Mar 11, 2015 at 12:27:59PM -0700, Jesse Barnes wrote:
> On 03/05/2015 09:37 PM, akash.goel@intel.com wrote:
> > +	/* Leaning on the below call to gen6_set_rps to program/setup the
> > +	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
> > +	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
> > +	dev_priv->rps.power = HIGH_POWER; /* force a reset */
> 
> Are you also sure that dev_priv->rps.cur_freq != min_freq_softlimit at
> this point?  That's the condition for calling into the threshold update
> function (maybe gen6_set_rps should check both variables though).

It's a good point, but Akash has inherited that bug from me. What I
think we want is removing the actual intel_set_rps() calls here (and the
rest of the *_enable_rps()) and do an intel_set_rps_idle() call from the
common point in the caller, where we can put all the dancing required to
force the RPS initialisation.
-Chris

-- 
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Re: [PATCH 07/11] drm/i915/skl: Updated the gen9_enable_rps function

[Jesse Barnes]

On 03/11/2015 12:46 PM, Chris Wilson wrote:
> On Wed, Mar 11, 2015 at 12:27:59PM -0700, Jesse Barnes wrote:
>> On 03/05/2015 09:37 PM, akash.goel@intel.com wrote:
>>> +	/* Leaning on the below call to gen6_set_rps to program/setup the
>>> +	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
>>> +	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
>>> +	dev_priv->rps.power = HIGH_POWER; /* force a reset */
>>
>> Are you also sure that dev_priv->rps.cur_freq != min_freq_softlimit at
>> this point?  That's the condition for calling into the threshold update
>> function (maybe gen6_set_rps should check both variables though).
> 
> It's a good point, but Akash has inherited that bug from me. What I
> think we want is removing the actual intel_set_rps() calls here (and the
> rest of the *_enable_rps()) and do an intel_set_rps_idle() call from the
> common point in the caller, where we can put all the dancing required to
> force the RPS initialisation.

Yeah, that would make things a little clearer.  I'd be fine with that as
a patch on top, fixing up the other functions as well.

Jesse

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Re: [PATCH 07/11] drm/i915/skl: Updated the gen9_enable_rps function

[Daniel Vetter]

On Wed, Mar 11, 2015 at 12:27:59PM -0700, Jesse Barnes wrote:
> On 03/05/2015 09:37 PM, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
> > to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
> > Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
> > us for older platforms. So updated the gen9_enable_rps function as per that.
> > 
> > v2: Updated to use new macro GT_INTERVAL_FROM_US
> > 
> > v3: Removed the initial setup of certain registers, from gen9_enable_rps,
> >     which gets overridden later from gen6_set_rps (Damien)
> > 
> > v4: Removed the enabling of rps interrupts, from gen9_enable_rps.
> >     To be done from intel_gen6_powersave_work only, as done for other
> >     platforms also.
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++++++---------------
> >  1 file changed, 13 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index c49950f..6273c282 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4132,23 +4132,21 @@ static void gen9_enable_rps(struct drm_device *dev)
> >  
> >  	gen6_init_rps_frequencies(dev);
> >  
> > -	I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
> > -	I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
> > -
> > -	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
> > -	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
> > -	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
> > -	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
> > -	I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
> > -	I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
> > +	/* Program defaults and thresholds for RPS*/
> > +	I915_WRITE(GEN6_RC_VIDEO_FREQ,
> > +		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
> > +
> > +	/* 1 second timeout*/
> > +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
> > +		GT_INTERVAL_FROM_US(dev_priv, 1000000));
> > +
> >  	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
> > -	I915_WRITE(GEN6_PMINTRMSK, 0x6);
> > -	I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
> > -		   GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
> > -		   GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
> > -		   GEN6_RP_DOWN_IDLE_AVG);
> >  
> > -	gen6_enable_rps_interrupts(dev);
> > +	/* Leaning on the below call to gen6_set_rps to program/setup the
> > +	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
> > +	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
> > +	dev_priv->rps.power = HIGH_POWER; /* force a reset */
> 
> Are you also sure that dev_priv->rps.cur_freq != min_freq_softlimit at
> this point?  That's the condition for calling into the threshold update
> function (maybe gen6_set_rps should check both variables though).

gen6 uses the same trick, so I hope it's safe. And indeed a bit there's a
call in both functions to gen6_init_rps_frequences which clears cur_freq
to 0. Not the clearest code though, maybe we should move that right to
above the call to gen6_set_rps. There's the added confusion that vlv/chv
works different.

Anyway that's material for a different patch, if at all.

> > +	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
> >  
> >  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> >  }
> > 
> 
> I'm assuming these match the latest SKL PM bits, but either way can be
> updated later based on tuning.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Merged up to this patch, still waiting for some final review on the
remaining ones.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH 08/11] drm/i915/skl: Updated the i915_frequency_info debugfs function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Added support for SKL in the i915_frequency_info debugfs function

v2:
- corrected the handling of reqf (Damien)
- Reorderd the platform check for cagf (Ville)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f9b5a97..e97de3cc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1090,7 +1090,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Current P-state: %d\n",
 			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
-		   IS_BROADWELL(dev)) {
+		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
 		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1109,11 +1109,15 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 		reqf = I915_READ(GEN6_RPNSWREQ);
-		reqf &= ~GEN6_TURBO_DISABLE;
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-			reqf >>= 24;
-		else
-			reqf >>= 25;
+		if (IS_GEN9(dev))
+			reqf >>= 23;
+		else {
+			reqf &= ~GEN6_TURBO_DISABLE;
+			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+				reqf >>= 24;
+			else
+				reqf >>= 25;
+		}
 		reqf = intel_gpu_freq(dev_priv, reqf);
 
 		rpmodectl = I915_READ(GEN6_RP_CONTROL);
@@ -1127,7 +1131,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		if (IS_GEN9(dev))
+			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
 		else
 			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
@@ -1153,7 +1159,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 		seq_printf(m, "Render p-state ratio: %d\n",
-			   (gt_perf_status & 0xff00) >> 8);
+			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
 		seq_printf(m, "Render p-state VID: %d\n",
 			   gt_perf_status & 0xff);
 		seq_printf(m, "Render p-state limit: %d\n",
@@ -1178,14 +1184,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   GEN6_CURBSYTAVG_MASK);
 
 		max_freq = (rp_state_cap & 0xff0000) >> 16;
+		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
 		max_freq = (rp_state_cap & 0xff00) >> 8;
+		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
 		max_freq = rp_state_cap & 0xff;
+		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
-- 
1.9.2

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Re: [PATCH 08/11] drm/i915/skl: Updated the i915_frequency_info debugfs function

[Ville Syrjälä]

On Fri, Mar 06, 2015 at 11:07:21AM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Added support for SKL in the i915_frequency_info debugfs function
> 
> v2:
> - corrected the handling of reqf (Damien)
> - Reorderd the platform check for cagf (Ville)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Had to dig up the PM docs for the GT_PERF_STATUS, but with the right
docs it all looks good to me.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
>  1 file changed, 17 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index f9b5a97..e97de3cc 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1090,7 +1090,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		seq_printf(m, "Current P-state: %d\n",
>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
>  	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> -		   IS_BROADWELL(dev)) {
> +		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
>  		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>  		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
>  		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> @@ -1109,11 +1109,15 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  		reqf = I915_READ(GEN6_RPNSWREQ);
> -		reqf &= ~GEN6_TURBO_DISABLE;
> -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -			reqf >>= 24;
> -		else
> -			reqf >>= 25;
> +		if (IS_GEN9(dev))
> +			reqf >>= 23;
> +		else {
> +			reqf &= ~GEN6_TURBO_DISABLE;
> +			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +				reqf >>= 24;
> +			else
> +				reqf >>= 25;
> +		}
>  		reqf = intel_gpu_freq(dev_priv, reqf);
>  
>  		rpmodectl = I915_READ(GEN6_RP_CONTROL);
> @@ -1127,7 +1131,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
>  		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
>  		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
> -		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +		if (IS_GEN9(dev))
> +			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> +		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
>  		else
>  			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> @@ -1153,7 +1159,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
>  		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>  		seq_printf(m, "Render p-state ratio: %d\n",
> -			   (gt_perf_status & 0xff00) >> 8);
> +			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
>  		seq_printf(m, "Render p-state VID: %d\n",
>  			   gt_perf_status & 0xff);
>  		seq_printf(m, "Render p-state limit: %d\n",
> @@ -1178,14 +1184,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   GEN6_CURBSYTAVG_MASK);
>  
>  		max_freq = (rp_state_cap & 0xff0000) >> 16;
> +		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
>  			   intel_gpu_freq(dev_priv, max_freq));
>  
>  		max_freq = (rp_state_cap & 0xff00) >> 8;
> +		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
>  			   intel_gpu_freq(dev_priv, max_freq));
>  
>  		max_freq = rp_state_cap & 0xff;
> +		max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
>  			   intel_gpu_freq(dev_priv, max_freq));
>  
> -- 
> 1.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 09/11] drm/i915/skl: Updated the act_freq_mhz_show sysfs function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Added support for SKL in the act_freq_mhz_show sysfs function

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 67bd07e..2476268 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -319,7 +319,9 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
 	} else {
 		u32 rpstat = I915_READ(GEN6_RPSTAT1);
-		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		if (IS_GEN9(dev_priv))
+			ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 			ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
 		else
 			ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
-- 
1.9.2

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[PATCH 10/11] drm/i915/skl: Enabling processing of Turbo interrupts

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Earlier Turbo interrupts were not being processed for SKL,
as something was amiss in turbo programming for SKL.
Now missing changes have been added, so enabling the Turbo
interrupt processing for SKL.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9baecb7..6b7cc10 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1696,11 +1696,6 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
  * the work queue. */
 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 {
-	/* TODO: RPS on GEN9+ is not supported yet. */
-	if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
-		      "GEN9+: unexpected RPS IRQ\n"))
-		return;
-
 	if (pm_iir & dev_priv->pm_rps_events) {
 		spin_lock(&dev_priv->irq_lock);
 		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
-- 
1.9.2

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Re: [PATCH 10/11] drm/i915/skl: Enabling processing of Turbo interrupts

[Jesse Barnes]

On 03/05/2015 09:37 PM, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Earlier Turbo interrupts were not being processed for SKL,
> as something was amiss in turbo programming for SKL.
> Now missing changes have been added, so enabling the Turbo
> interrupt processing for SKL.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9baecb7..6b7cc10 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1696,11 +1696,6 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
>   * the work queue. */
>  static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
>  {
> -	/* TODO: RPS on GEN9+ is not supported yet. */
> -	if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
> -		      "GEN9+: unexpected RPS IRQ\n"))
> -		return;
> -
>  	if (pm_iir & dev_priv->pm_rps_events) {
>  		spin_lock(&dev_priv->irq_lock);
>  		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 11/11] drm/i915/skl: Enable the RPS interrupts programming

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Enable the RPS interrupts programming(enable/disable/reset) for GEN9,
as missing changes to enable the RPS support on GEN9 have been added.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6273c282..3692837 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5629,12 +5629,7 @@ static void gen6_suspend_rps(struct drm_device *dev)
 
 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 
-	/*
-	 * TODO: disable RPS interrupts on GEN9+ too once RPS support
-	 * is added for it.
-	 */
-	if (INTEL_INFO(dev)->gen < 9)
-		gen6_disable_rps_interrupts(dev);
+	gen6_disable_rps_interrupts(dev);
 }
 
 /**
@@ -5692,12 +5687,7 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
-	/*
-	 * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
-	 * added for it.
-	 */
-	if (INTEL_INFO(dev)->gen < 9)
-		gen6_reset_rps_interrupts(dev);
+	gen6_reset_rps_interrupts(dev);
 
 	if (IS_CHERRYVIEW(dev)) {
 		cherryview_enable_rps(dev);
@@ -5716,8 +5706,7 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 	}
 	dev_priv->rps.enabled = true;
 
-	if (INTEL_INFO(dev)->gen < 9)
-		gen6_enable_rps_interrupts(dev);
+	gen6_enable_rps_interrupts(dev);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
-- 
1.9.2

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Re: [PATCH 11/11] drm/i915/skl: Enable the RPS interrupts programming

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5902
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              280/280              279/280
ILK                                  308/308              308/308
SNB                 -21              328/328              307/328
IVB                                  379/379              379/379
BYT                                  294/294              294/294
HSW                 -2              387/387              385/387
BDW                 -1              316/316              315/316
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_userptr_blits_minor-unsync-normal      DMESG_WARN(1)PASS(6)      DMESG_WARN(1)PASS(1)
 SNB  igt_kms_cursor_crc_cursor-size-change      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(2)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(3)DMESG_WARN(1)PASS(4)      NSPT(2)
 SNB  igt_pm_rpm_cursor      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_fences      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_fences-dpms      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(3)DMESG_WARN(1)PASS(3)      NSPT(2)
 SNB  igt_pm_rpm_gem-pread      NSPT(3)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_i2c      NSPT(3)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(3)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(3)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(3)DMESG_WARN(1)PASS(1)      NSPT(2)
 SNB  igt_pm_rpm_rte      NSPT(3)DMESG_WARN(1)PASS(1)      NSPT(2)
*HSW  igt_gem_seqno_wrap      PASS(2)      DMESG_WARN(1)PASS(1)
*HSW  igt_gem_storedw_loop_blt      PASS(2)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(7)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 11/11] drm/i915/skl: Enable the RPS interrupts programming

[Jesse Barnes]

On 03/05/2015 09:37 PM, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Enable the RPS interrupts programming(enable/disable/reset) for GEN9,
> as missing changes to enable the RPS support on GEN9 have been added.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 17 +++--------------
>  1 file changed, 3 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6273c282..3692837 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5629,12 +5629,7 @@ static void gen6_suspend_rps(struct drm_device *dev)
>  
>  	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
>  
> -	/*
> -	 * TODO: disable RPS interrupts on GEN9+ too once RPS support
> -	 * is added for it.
> -	 */
> -	if (INTEL_INFO(dev)->gen < 9)
> -		gen6_disable_rps_interrupts(dev);
> +	gen6_disable_rps_interrupts(dev);
>  }
>  
>  /**
> @@ -5692,12 +5687,7 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  
> -	/*
> -	 * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
> -	 * added for it.
> -	 */
> -	if (INTEL_INFO(dev)->gen < 9)
> -		gen6_reset_rps_interrupts(dev);
> +	gen6_reset_rps_interrupts(dev);
>  
>  	if (IS_CHERRYVIEW(dev)) {
>  		cherryview_enable_rps(dev);
> @@ -5716,8 +5706,7 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>  	}
>  	dev_priv->rps.enabled = true;
>  
> -	if (INTEL_INFO(dev)->gen < 9)
> -		gen6_enable_rps_interrupts(dev);
> +	gen6_enable_rps_interrupts(dev);
>  
>  	mutex_unlock(&dev_priv->rps.hw_lock);
>  
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 11/11] drm/i915/skl: Enable the RPS interrupts programming

[Daniel Vetter]

On Wed, Mar 11, 2015 at 02:12:02PM -0700, Jesse Barnes wrote:
> On 03/05/2015 09:37 PM, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > Enable the RPS interrupts programming(enable/disable/reset) for GEN9,
> > as missing changes to enable the RPS support on GEN9 have been added.
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 17 +++--------------
> >  1 file changed, 3 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 6273c282..3692837 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5629,12 +5629,7 @@ static void gen6_suspend_rps(struct drm_device *dev)
> >  
> >  	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> >  
> > -	/*
> > -	 * TODO: disable RPS interrupts on GEN9+ too once RPS support
> > -	 * is added for it.
> > -	 */
> > -	if (INTEL_INFO(dev)->gen < 9)
> > -		gen6_disable_rps_interrupts(dev);
> > +	gen6_disable_rps_interrupts(dev);
> >  }
> >  
> >  /**
> > @@ -5692,12 +5687,7 @@ static void intel_gen6_powersave_work(struct work_struct *work)
> >  
> >  	mutex_lock(&dev_priv->rps.hw_lock);
> >  
> > -	/*
> > -	 * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
> > -	 * added for it.
> > -	 */
> > -	if (INTEL_INFO(dev)->gen < 9)
> > -		gen6_reset_rps_interrupts(dev);
> > +	gen6_reset_rps_interrupts(dev);
> >  
> >  	if (IS_CHERRYVIEW(dev)) {
> >  		cherryview_enable_rps(dev);
> > @@ -5716,8 +5706,7 @@ static void intel_gen6_powersave_work(struct work_struct *work)
> >  	}
> >  	dev_priv->rps.enabled = true;
> >  
> > -	if (INTEL_INFO(dev)->gen < 9)
> > -		gen6_enable_rps_interrupts(dev);
> > +	gen6_enable_rps_interrupts(dev);
> >  
> >  	mutex_unlock(&dev_priv->rps.hw_lock);
> >  
> > 
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Merged the remaining four, thanks for patches&review.
-Daniel
-- 
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH v4 00/11] Added missing changes for Turbo feature on SKL

[Jesse Barnes]

On 03/05/2015 09:37 PM, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> This patch series add the missing changes, required for proper
> functioning of the Turbo feature on SKL. Most of the changes are
> mainly due to the fact that on SKL, the frequency has to be programmed
> in units of 16.66 MHZ and the time period value programmed in Up/Down
> EI & threshold registers, is in units of 1.333 micro seconds.
> In this version, review comments from Chris & Ville have been addressed
> and a new patch has been added to enable the RPS interrupts programming
> for SKL also.
> 
> Akash Goel (11):
>   drm/i915/skl: Added new macros
>   drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()
>   drm/i915/skl: Updated the gen6_init_rps_frequencies function
>   drm/i915/skl: Updated the gen6_set_rps function
>   drm/i915/skl: Restructured the gen6_set_rps_thresholds function
>   drm/i915/skl: Updated the gen6_rps_limits function
>   drm/i915/skl: Updated the gen9_enable_rps function
>   drm/i915/skl: Updated the i915_frequency_info debugfs function
>   drm/i915/skl: Updated the act_freq_mhz_show sysfs function
>   drm/i915/skl: Enabling processing of Turbo interrupts
>   drm/i915/skl: Enable the RPS interrupts programming
> 
>  drivers/gpu/drm/i915/i915_debugfs.c |  25 ++++--
>  drivers/gpu/drm/i915/i915_drv.h     |   1 +
>  drivers/gpu/drm/i915/i915_irq.c     |   5 --
>  drivers/gpu/drm/i915/i915_reg.h     |   9 +++
>  drivers/gpu/drm/i915/i915_sysfs.c   |   4 +-
>  drivers/gpu/drm/i915/intel_pm.c     | 147 ++++++++++++++++++------------------
>  6 files changed, 105 insertions(+), 86 deletions(-)

It looks like turbo is working, but the pm_rps test is still having a
little trouble.  I patched this on top to make it happier, but there are
still problems with the test getting to the expected frequencies, please
check out https://bugs.freedesktop.org/show_bug.cgi?id=89123.

--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6696,7 +6696,8 @@ static int chv_freq_opcode(struct drm_i915_private
*dev_pr
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
        if (IS_GEN9(dev_priv->dev))
-               return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
+               return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
+                       GEN9_FREQ_SCALER);
        else if (IS_CHERRYVIEW(dev_priv->dev))
                return chv_gpu_freq(dev_priv, val);
        else if (IS_VALLEYVIEW(dev_priv->dev))
@@ -6708,7 +6709,8 @@ int intel_gpu_freq(struct drm_i915_private
*dev_priv, int
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
        if (IS_GEN9(dev_priv->dev))
-               return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
+               return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
+                       GT_FREQUENCY_MULTIPLIER);
        else if (IS_CHERRYVIEW(dev_priv->dev))
                return chv_freq_opcode(dev_priv, val);
        else if (IS_VALLEYVIEW(dev_priv->dev))


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