From: Daniel Vetter <daniel@ffwll.ch>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: Detect page faults during hangcheck
Date: Mon, 16 Mar 2015 18:53:40 +0100 [thread overview]
Message-ID: <20150316175340.GL21993@phenom.ffwll.local> (raw)
In-Reply-To: <1426513596-11338-3-git-send-email-mika.kuoppala@intel.com>
On Mon, Mar 16, 2015 at 03:46:35PM +0200, Mika Kuoppala wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> On Sandybridge+, the GPU provides the ERROR register for detecting page
> faults. Hook this up to our hangcheck so that we can dump the error
> state soon after such an event occurs. This would be better inside an
> interrupt handler, but it serves a purpose here as it detects that our
> initial context setup is invalid...
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 5 +++++
> drivers/gpu/drm/i915/intel_uncore.c | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 49ad5fb..ea668fc 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2929,6 +2929,11 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> if (!i915.enable_hangcheck)
> return;
>
> + if (INTEL_INFO(dev_priv)->gen >= 6 && I915_READ(ERROR_GEN6)) {
> + i915_handle_error(dev, false, "GPU reported a page fault");
> + I915_WRITE(ERROR_GEN6, 0);
Shouldn't we also at least report the bits from the ERROR register
somewhere? Or are they supremely useless?
-Daniel
> + }
> +
> for_each_ring(ring, dev_priv, i) {
> u64 acthd;
> u32 seqno;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ab5cc94..c58535e 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -359,6 +359,8 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
> if (IS_GEN6(dev) || IS_GEN7(dev))
> __raw_i915_write32(dev_priv, GTFIFODBG,
> __raw_i915_read32(dev_priv, GTFIFODBG));
> + if (INTEL_INFO(dev)->gen >= 6)
> + __raw_i915_write32(dev_priv, ERROR_GEN6, 0);
>
> intel_uncore_forcewake_reset(dev, restore_forcewake);
> }
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Intel-gfx mailing list
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next prev parent reply other threads:[~2015-03-16 17:51 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-16 13:46 [PATCH 0/3] ring/context initialization patches Mika Kuoppala
2015-03-16 13:46 ` [PATCH 1/3] drm/i915: Wait for render state init Mika Kuoppala
2015-03-16 13:51 ` Chris Wilson
2015-03-16 14:20 ` Mika Kuoppala
2015-03-16 14:38 ` Chris Wilson
2015-03-16 15:56 ` Mika Kuoppala
2015-03-16 15:58 ` [PATCH] drm/i915: Push mm switch immediately to ring Mika Kuoppala
2015-03-16 21:35 ` Chris Wilson
2015-03-17 16:10 ` Mika Kuoppala
2015-03-16 13:46 ` [PATCH 2/3] drm/i915: Detect page faults during hangcheck Mika Kuoppala
2015-03-16 17:53 ` Daniel Vetter [this message]
2015-03-16 21:30 ` Chris Wilson
2015-03-17 10:31 ` Daniel Vetter
2015-03-16 13:46 ` [PATCH 3/3] drm/i915: Reorder hw init to avoid executing with invalid context/mm state Mika Kuoppala
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