From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [RFC v5 9/9] drm/i915: Backlight control using CRC PMIC based PWM driver Date: Tue, 24 Mar 2015 09:59:38 +0100 Message-ID: <20150324085937.GC17183@ulmo.nvidia.com> References: <1426177893-17945-1-git-send-email-shobhit.kumar@intel.com> <1426177893-17945-10-git-send-email-shobhit.kumar@intel.com> <20150313143043.GF17419@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2032232040==" Return-path: Received: from mail-pa0-f50.google.com (mail-pa0-f50.google.com [209.85.220.50]) by gabe.freedesktop.org (Postfix) with ESMTP id EFCF96E693 for ; Tue, 24 Mar 2015 01:59:42 -0700 (PDT) Received: by padcy3 with SMTP id cy3so219451574pad.3 for ; Tue, 24 Mar 2015 01:59:42 -0700 (PDT) In-Reply-To: <20150313143043.GF17419@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?utf-8?B?U3lyasOkbMOk?= Cc: Alexandre Courbot , Samuel Ortiz , Jani Nikula , Shobhit Kumar , intel-gfx , Daniel Vetter , Linus Walleij List-Id: intel-gfx@lists.freedesktop.org --===============2032232040== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="E/DnYTRukya0zdZ1" Content-Disposition: inline --E/DnYTRukya0zdZ1 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Mar 13, 2015 at 04:30:43PM +0200, Ville Syrj=C3=A4l=C3=A4 wrote: > On Thu, Mar 12, 2015 at 10:01:33PM +0530, Shobhit Kumar wrote: > > CC: Samuel Ortiz > > Cc: Linus Walleij > > Cc: Alexandre Courbot > > Cc: Thierry Reding > > Signed-off-by: Shobhit Kumar > > --- > > drivers/gpu/drm/i915/intel_dsi.c | 25 +++++++++++++++++++++++++ > > drivers/gpu/drm/i915/intel_dsi.h | 3 +++ > > 2 files changed, 28 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/in= tel_dsi.c > > index 219421c..511446f 100644 > > --- a/drivers/gpu/drm/i915/intel_dsi.c > > +++ b/drivers/gpu/drm/i915/intel_dsi.c > > @@ -32,6 +32,7 @@ > > #include > > #include > > #include > > +#include > > #include "i915_drv.h" > > #include "intel_drv.h" > > #include "intel_dsi.h" > > @@ -402,6 +403,10 @@ static void intel_dsi_enable(struct intel_encoder = *encoder) > > =20 > > intel_dsi_port_enable(encoder); > > } > > + > > + /* Enable the backlight with default PWM as programmed by BIOS */ > > + pwm_enable(intel_dsi->pwm); > > + pwm_config_alternate(intel_dsi->pwm, 0x7F, 100); >=20 > I suppose we migth want to wrap these in 'if (intel_dsi->pwm)' checks, > or does the pwm subsystem take care of NULL checks for us? The PWM core checks for valid PWM devices and will return an error if you pass in an invalid device. What this is completely missing is any kind of error checking. But perhaps you don't care about failure here for this particular platform? It would be useful to debug issues with black screens and such I can imagine. Also, though it's admittedly somewhat underdocumented, the typical sequence of calls should be pwm_config() followed by pwm_enable(). The reason is that some devices don't support being configured while enabled. But you may not care about this here since you're always dealing with a fixed device anyway. Thierry --E/DnYTRukya0zdZ1 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJVESd4AAoJEN0jrNd/PrOhH0YP/j5jK8wOSol9BSkklZpnviB0 dzwZoVjdWkigNgWgEYvH/qqAjfOV+t1p+OwDumiqasU/lJIyfn5M3NmnDyKr/ixL ypVmf3/7pmihezPfLtYC9chzdJKzNzyR1Ge+0ffFxRyc+2SWLkvT6sjtVZSBIM1w 6Ev9ouMRzCsreibKsCzXVyT00GUlVZGN6l8Pe5cSZcTy5WprhD8dW5kssPNzKCLf 4ySbfU9KVYiqLtAK1YV3ARZNXVfkdq6lf2XxbjSGs/QaR0C0RD0yp/bDgaZNMf6Y w06BuSsV2BDUyawN2mfu++8/Di0KbQtG6v8U04raG7wG5IaOQjBqYnHMsjvgydtd 1iC9yUgoOxOhBgsTaJLpkicpNcMFokZEGOQILcZQpLLNLwUR10ZD3usgEiXStYZY PREDd1PX3Hq0+SSqVSEbkx9JcCF1pgk9R0OMrBoVS3pweYbtAQye6iJGJTxJ1SQI 2YgjX1Hov8/sYn7YmDIr9TnWvS7WztmdYsb5Cgs+cO5i9oE+HKVjAkgPM8HVG9sp 0yuvosAceqhXuuEAQdXud+/oIVuVm73weQAfmkLSuw/nFfrfblWEcdNxXXJT5Ht1 HI3VwGPVI6IYeMWm6+KKvdilLImm9g1+VWuXVCGwMgCDL7hdfgrcQfObiVeXwj/+ An4OXJlGEWqD2jmnvrk9 =72PL -----END PGP SIGNATURE----- --E/DnYTRukya0zdZ1-- --===============2032232040== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK --===============2032232040==--