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From: Daniel Vetter <daniel@ffwll.ch>
To: Ramalingam C <ramalingam.c@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 2/2] drm/i915: Only enabled DRRS if PRS won't be enabled on this pipe.
Date: Mon, 30 Mar 2015 17:39:54 +0200	[thread overview]
Message-ID: <20150330153954.GA6354@phenom.ffwll.local> (raw)
In-Reply-To: <55191C29.5020801@intel.com>

On Mon, Mar 30, 2015 at 03:19:29PM +0530, Ramalingam C wrote:
> Looks good to me..
> 
> Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> 
> On Friday 27 March 2015 12:51 AM, Rodrigo Vivi wrote:
> >With PSR enabled being pre computed on pipe_config we can now
> >prevent DRRS to be enabled along with PSR.
> >
> >v2: Rebase after changing previous patch
> >
> >Cc: Ramalingam C <ramalingam.c@intel.com>
> >Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Both patches applied, thanks.
-Daniel

> >---
> >  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >index e6b1c42..5551b3c 100644
> >--- a/drivers/gpu/drm/i915/intel_dp.c
> >+++ b/drivers/gpu/drm/i915/intel_dp.c
> >@@ -4994,11 +4994,6 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> >  		return;
> >  	}
> >-	/*
> >-	 * FIXME: This needs proper synchronization with psr state for some
> >-	 * platforms that cannot have PSR and DRRS enabled at the same time.
> >-	 */
> >-
> >  	dig_port = dp_to_dig_port(intel_dp);
> >  	encoder = &dig_port->base;
> >  	intel_crtc = encoder->new_crtc;
> >@@ -5084,6 +5079,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> >  		return;
> >  	}
> >+	if (intel_crtc->config->psr_ready) {
> >+		DRM_DEBUG_KMS("DRRS: PSR will be enabled on this crtc\n");
> >+		return;
> >+	}
> >+
> >  	mutex_lock(&dev_priv->drrs.mutex);
> >  	if (WARN_ON(dev_priv->drrs.dp)) {
> >  		DRM_ERROR("DRRS already enabled\n");
> 
> -- 
> Thanks,
> --Ram
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-03-30 15:38 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-24 19:12 [PATCH 1/2] drm/i915: Add psr_enabled on pipe_config Rodrigo Vivi
2015-03-24 19:12 ` [PATCH 2/2] drm/i915: Only enabled DRRS if PRS won't be enabled on this pipe Rodrigo Vivi
2015-03-24 23:17   ` shuang.he
2015-03-25 10:38   ` Ramalingam C
2015-03-25 15:41     ` Vivi, Rodrigo
2015-03-26 14:39       ` Ramalingam C
2015-03-26 19:21         ` Rodrigo Vivi
2015-03-30  9:49           ` Ramalingam C
2015-03-30 15:39             ` Daniel Vetter [this message]
2015-03-31 13:34               ` Daniel Vetter
2015-03-25  7:04 ` [PATCH 1/2] drm/i915: Add psr_enabled on pipe_config Sivakumar Thulasimani
2015-03-25 20:21   ` Rodrigo Vivi
2015-03-26 14:50 ` Ramalingam C
2015-03-26 19:20   ` [PATCH 1/2] drm/i915: Add psr_ready " Rodrigo Vivi
2015-03-27  6:07     ` Sivakumar Thulasimani
2015-03-27  8:32       ` Daniel Vetter
2015-03-27  9:00         ` Sivakumar Thulasimani
2015-03-30  9:50     ` Ramalingam C
  -- strict thread matches above, loose matches on Subject: below --
2015-04-15 16:38 Rodrigo Vivi
2015-04-15 16:38 ` [PATCH 2/2] drm/i915: Only enabled DRRS if PRS won't be enabled on this pipe Rodrigo Vivi
2015-04-16 11:49   ` shuang.he

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