From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
Date: Wed, 1 Apr 2015 18:41:32 +0300 [thread overview]
Message-ID: <20150401154132.GU17410@intel.com> (raw)
In-Reply-To: <1427843001-2411-1-git-send-email-rodrigo.vivi@intel.com>
On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> Program the default initial value of the L3SqcReg1 on BDW for performance
>
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
>
> v3: Spec shows now a different value. It tells us to set to 0x784000
> instead the 0x610000 that is there already.
> Also rebased after a long time so using WA_WRITE now.
>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e1a0fd9..7f8b69a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
> #define GEN7_L3SQCREG1 0xB010
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> +#define GEN8_L3SQCREG1 0xB100
> +#define BDW_WA_L3SQCREG1_DEFAULT 0x784000
> +
> #define GEN7_L3CNTLREG1 0xB01C
> #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
> #define GEN7_L3AGDIS (1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index abe062a..c02fccc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> GEN6_WIZ_HASHING_MASK,
> GEN6_WIZ_HASHING_16x4);
>
> + /* WaProgramL3SqcReg1Default:bdw */
> + WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
> return 0;
> }
>
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-04-01 15:41 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-31 23:03 [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default Rodrigo Vivi
2015-04-01 5:52 ` shuang.he
2015-04-01 7:49 ` Jani Nikula
2015-04-01 8:31 ` Ville Syrjälä
2015-04-01 14:49 ` Vivi, Rodrigo
2015-04-01 15:41 ` Ville Syrjälä [this message]
2015-04-07 8:26 ` Daniel Vetter
-- strict thread matches above, loose matches on Subject: below --
2014-09-26 19:06 [PATCH 3/5] " Ville Syrjälä
2014-09-30 15:11 ` [PATCH] " Rodrigo Vivi
2014-10-01 13:46 ` Mika Kuoppala
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